Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 12/01/2021
Public

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3.3.2. Supported Simulators

The following tables show supported simulators for MCDMA example designs.
Note: Root Port mode simulation is supported by VCS simulator only.
Table 14.  Supported Simulators for MCDMA H-Tile
Example Design Questa*-Intel® FPGA Edition Modelsim VCS VCS MX Xcelium*
PIO No Yes Yes Yes Yes
AVMM DMA No4 Yes Yes Yes Yes
Device-side Packet Loopback No4 Yes Yes Yes Yes
Packet Generate/Check No4 Yes Yes Yes Yes
Table 15.  Supported Simulators for MCDMA P-Tile and F-Tile
Example Design Questa*-Intel® FPGA Edition Modelsim VCS VCS MX Xcelium*
PIO5 Yes Yes Yes Yes No4
AVMM DMA No4 No4 Yes Yes No4
Device-side Packet Loopback No4 No4 Yes Yes No4
Packet Generate/Check No4 No4 Yes Yes No4
Traffic Generator/Checker No4 No4 Yes Yes No4

* If you select BAM, BAM+BAS, and BAM+MCDMA modes, enable BAR2 (for example, 64KB) in the IP Parameter Editor when generating the PIO example design.

4 These example design and simulators may be supported in future release.
5 When you generate a PIO example design with BAM, BAM+BAS, or BAM+MCDMA user mode selected, enable BAR2 (for example: 64KB) in the IP Parameter Editor before you generate the example design.

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