Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 12/01/2021
Public

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2.4.2. Single-Port Avalon-ST Packet Generate/Check

Below is the block diagram of a packet generator design example with a single-port Avalon Streaming interface supporting multiple channels without any interleaving. This design example can be used with the perfq application to evaluate the functionality and capture the MCDMA performance. In the H2D direction, the design example checks for the received packets and software then reads the status registers to make sure there are no errors. In the D2H direction, the design example generates the packets and forwards them to the Host side by means of PCIe MWr.

For a description of which driver(s) to use with this design example, refer to Driver Support.

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