Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 12/01/2021
Public

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3.5.2.4.3.2. BAM Test

  1. If the BAM support is enabled on hardware, enable the following flags in: user/common/mk/common.mk
    __cflags += -UIFC_PIO_256 > 256b read/write operations on PIO BAR 
    	__cflags += -UIFC_PIO_128 > 128b read/write operations on PIO BAR
  2. Enable the below flag for 256b read or write operations in: user/common/mk/common.mk
    __cflags += -DIFC_PIO_256
    Command: ./cli/perfq_app/perfq_app -b 0000:01:00.0 -o
    Figure 45. PIO 256 Write and Read Test
  3. Enable the below flag for 128b read or write operations in: user/common/mk/common.mk
    __cflags += -DIFC_PIO_128 
    __cflags += -UIFC_PIO_256
    Command: ./perfq_app -b 0000:01:00.0 -o
    Figure 46. PIO 128b Write and Read Test

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