Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 12/01/2021
Public

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3.3.4. Run the Simulation Script

Figure 38. Simulation Script
  1. Change to the testbench simulation directory, pcie_ed_tb/pcie_ed_tb/sim/<simulators> .
  2. Run the simulation script for the simulator of your choice. Refer to the table below.
  3. Analyze the results.
The following tables show supported simulators for MCDMA example designs.
Note: Root Port mode simulation is supported by VCS simulator only.
Table 16.  Supported Simulators for MCDMA H-Tile
Example Design Questa*-Intel® FPGA Edition Modelsim VCS VCS MX Xcelium*
PIO No Yes Yes Yes Yes
AVMM DMA No6 Yes Yes Yes Yes
Device-side Packet Loopback No6 Yes Yes Yes Yes
Packet Generate/Check No6 Yes Yes Yes Yes
Table 17.  Supported Simulators for MCDMA P-Tile and F-Tile
Example Design Questa*-Intel® FPGA Edition Modelsim VCS VCS MX Xcelium*
PIO7 Yes Yes Yes Yes No6
AVMM DMA No6 No6 Yes Yes No6
Device-side Packet Loopback No6 No6 Yes Yes No6
Packet Generate/Check No6 No6 Yes Yes No6
Traffic Generator/Checker No6 No6 Yes Yes No6
Table 18.  Steps to run the simulation
Simulator Simulation Directory Instructions
ModelSim

<example_design>/pcie_ed_tb/ pcie_ed _tb/sim/mentor/

  1. Invoke vsim (by typing vsim, which brings up a console window where you can run the following commands).
  2. do msim_setup.tcl
    Note: Alternatively, instead of doing Steps 1 and 2, you can type: vsim -c -do msim_setup.tcl
  3. ld_debug
  4. run -all
  5. A successful simulation ends with the following message: "Simulation stopped due to successful completion!"
Note: ModelSim currently supports BAM and PIO example designs only.
VCS/VCSMX

<example_design> /pcie_ed_tb/ pcie_ed _tb/sim/synopsys/vcs

<example_design>/pcie_ed_tb/pcie_ed _tb/sim/synopsys/vcsmx

  1. sh vcs_setup.sh 
    USER_DEFINED_COMPILE_OPTIONS="" 
    USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" 
    USER_DEFINED_SIM_OPTIONS=""
  2. A successful simulation ends with the following message: "Simulation stopped due to successful completion!"
Xcelium

<example_design>/pcie_ed_tb/pcie_ed_tb/sim/xcelium

  1. sh xcelium_setup.sh 
    USER_DEFINED_SIM_OPTIONS="" 
    USER_DEFINED_ELAB_OPTIONS ="-timescale\ 1ns/1ps\ -NOWARN\ CSINFI"
  2. A successful simulation ends with the following message: "Simulation stopped due to successful completion!"
Note: Xcelium currently support for H-Tile only
6 These example design and simulators may be supported in future release.
7 When you generate a PIO example design with BAM, BAM+BAS, or BAM+MCDMA user mode selected, enable BAR2 (for example: 64KB) in the IP Parameter Editor before you generate the example design.

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