Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

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ID 683517
Date 12/01/2021
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Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Design Example Detailed Description 3. Design Example Quick Start Guide 4. Multi Channel DMA for FPGA IP Design Example User Guide Archives 5. Document Revision History for the Multi Channel DMA for FPGA IP Design Example User Guide
2. Design Example Detailed Description x
2.1. Design Example Overview 2.2. Hardware and Software Requirements 2.3. PIO Using MCDMA Bypass Mode 2.4. Avalon-ST Packet Generate/Check 2.5. Avalon-ST Device-side Packet Loopback 2.6. Avalon-MM DMA 2.7. Traffic Generator and Checker
2.3. PIO Using MCDMA Bypass Mode x
2.3.1. Avalon-ST PIO Using MCDMA Bypass Mode 2.3.2. Avalon-MM PIO Using MCDMA Bypass mode
2.3.1. Avalon-ST PIO Using MCDMA Bypass Mode x
2.3.1.1. Four-Port Avalon-ST PIO Using MCDMA Bypass Mode 2.3.1.2. Single-Port Avalon-ST PIO Using MCDMA Bypass Mode
2.3.1.1. Four-Port Avalon-ST PIO Using MCDMA Bypass Mode x
2.3.1.1.1. Simulation Result 2.3.1.1.2. Hardware Test Result
2.3.2. Avalon-MM PIO Using MCDMA Bypass mode x
2.3.2.1. Simulation Results 2.3.2.2. Hardware Test Results
2.4. Avalon-ST Packet Generate/Check x
2.4.1. Four-Port Avalon-ST Packet Generate/Check 2.4.2. Single-Port Avalon-ST Packet Generate/Check
2.4.1. Four-Port Avalon-ST Packet Generate/Check x
2.4.1.1. Simulation Results 2.4.1.2. Hardware Test Results
2.4.2. Single-Port Avalon-ST Packet Generate/Check x
2.4.2.1. Simulation Waveforms 2.4.2.2. Simulation Log
2.5. Avalon-ST Device-side Packet Loopback x
2.5.1. Simulation Results 2.5.2. Hardware Test Results
2.6. Avalon-MM DMA x
2.6.1. Simulation Results 2.6.2. Hardware Test Results
2.7. Traffic Generator and Checker x
2.7.1. Traffic Generator and checker Example Design Register Map
3. Design Example Quick Start Guide x
3.1. Design Example Directory Structure 3.2. Generating the Example Design using Intel® Quartus® Prime 3.3. Simulating the Design Example 3.4. Compiling the Example Design in Intel® Quartus® Prime 3.5. Running the Design Example Application on a Hardware Setup
3.2. Generating the Example Design using Intel® Quartus® Prime x
3.2.1. Procedure
3.3. Simulating the Design Example x
3.3.1. Testbench Overview 3.3.2. Supported Simulators 3.3.3. Example Testbench Flow for DMA Test with Avalon-ST Packet Generate/Check Design Example 3.3.4. Run the Simulation Script 3.3.5. View the Results
3.5. Running the Design Example Application on a Hardware Setup x
3.5.1. Program the FPGA 3.5.2. Quick Start Guide
3.5.2. Quick Start Guide x
3.5.2.1. Software Test Setup 3.5.2.2. Driver Support 3.5.2.3. MCDMA Custom Driver 3.5.2.4. MCDMA DPDK Poll Mode Driver 3.5.2.5. MCDMA Kernel Mode Character Device Driver 3.5.2.6. MCDMA Kernel Mode Network Device Driver
3.5.2.3. MCDMA Custom Driver x
3.5.2.3.1. Prerequisites 3.5.2.3.2. Software Setup 3.5.2.3.3. Run the Reference Example Application 3.5.2.3.4. 2K Channels Test with DIDF Mode
3.5.2.3.1. Prerequisites x
3.5.2.3.1.1. Configuration Changes from BIOS 3.5.2.3.1.2. External Packages 3.5.2.3.1.3. Set the Boot Parameters
3.5.2.3.2. Software Setup x
3.5.2.3.2.1. Installing the Linux Kernel Driver and Enabling VFs 3.5.2.3.2.2. Build and Install User Space Library 3.5.2.3.2.3. Create Guest VM by Using QEMU 3.5.2.3.2.4. Establish Communication Between Host and QEMU
3.5.2.3.3. Run the Reference Example Application x
3.5.2.3.3.1. Meta Data Test 3.5.2.3.3.2. BAM Test 3.5.2.3.3.3. BAS Test 3.5.2.3.3.4. Packet Gen Test
3.5.2.4. MCDMA DPDK Poll Mode Driver x
3.5.2.4.1. Prerequisites 3.5.2.4.2. Install PMD and Test Application 3.5.2.4.3. Run the Reference Example Application
3.5.2.4.1. Prerequisites x
3.5.2.4.1.1. Set the Boot Parameters 3.5.2.4.1.2. Configuration Changes from BIOS 3.5.2.4.1.3. Install and Build Testpmd
3.5.2.4.2. Install PMD and Test Application x
3.5.2.4.2.1. Create VM Environment
3.5.2.4.3. Run the Reference Example Application x
3.5.2.4.3.1. Example of Verifying on an AVMM Design 3.5.2.4.3.2. BAM Test 3.5.2.4.3.3. BAS Test
3.5.2.5. MCDMA Kernel Mode Character Device Driver x
3.5.2.5.1. Prerequisites 3.5.2.5.2. Software Setup 3.5.2.5.3. Examples
3.5.2.5.1. Prerequisites x
3.5.2.5.1.1. Host Configuration 3.5.2.5.1.2. Set the Boot Parameters
3.5.2.5.2. Software Setup x
3.5.2.5.2.1. Build and Install Kernel Driver 3.5.2.5.2.2. Build and Install Libmcmem 3.5.2.5.2.3. Build Testapp 3.5.2.5.2.4. Configure Kernel Driver 3.5.2.5.2.5. Configure Libmcmem 3.5.2.5.2.6. Configure Testapp
3.5.2.6. MCDMA Kernel Mode Network Device Driver x
3.5.2.6.1. Build and Install Netdev Driver 3.5.2.6.2. Configure the Device Communication 3.5.2.6.3. Test Procedure by Using Name Space Environment
1. Terms and Acronyms
2. Design Example Detailed Description
3. Design Example Quick Start Guide
4. Multi Channel DMA for FPGA IP Design Example User Guide Archives
5. Document Revision History for the Multi Channel DMA for FPGA IP Design Example User Guide

2.7.1. Traffic Generator and checker Example Design Register Map

The control and status registers of the traffic generator and checker are byte addresses and must be Avalon-MM word aligned (for example, bits [5:0] are assumed to be set to 0 for x16 (OR) bits [4:0] are assumed to be set to 0 for x8).
Table 3.  Read start address (Offset 16’h0000)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31:0] RAdd R/W 0 This register contains the base addresses that the Traffic Checker reads from.
Table 4.  Read count (Offset 16’h0001)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31] Mode R/W 0

0: Fixed no of transfers

1: non-stop transfers
[30:12] rsvd     Reserved
[11:0] RCnt R/W 0 Write to the RCnt registers to specify the number of transfers to execute. Reading from one of these registers returns the number of transfers that have occurred since it was last read.
Table 5.  Read error count (Offset 16’h0002)
Bit[63:0] Name R/W Default Description
[63:12] rsvd     Reserved
[11:0] RErr ROC 0 Reading the RErr register returns the number of errors detected since the register was last read. A maximum of one error is counted per clock cycle.
Table 6.  Read control (Offset 16’h0003)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31] enable R/W 0 0: stop 1: start
[30:8] rsvd     Reserved
[7:0] transfer_size   0 This register configures the burst length per transfer (ideal value for x16 is 8 & x8 is 16). Zero is not a legal value.
Table 7.  Write start address (Offset 16’h0004)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31:0] WAdd R/W 0 This register contains the base addresses that the Traffic Generator writes to.
Table 8.  Write count (Offset 16’h0005)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31] Mode R/W 0

0: Fixed no of transfers

1: non-stop transfers
[30:12] rsvd     Reserved
[11:0] WCnt R/W 0 Write to the WCnt registers to specify the number of transfers to execute. Reading from one of these registers returns the number of transfers that have occurred since it was last read.
Table 9.  Write error count (Offset 16’h0006)
Bit[63:0] Name R/W Default Description
[63:12] rsvd     Reserved
[11:0] WErr ROC 0 Reserved (Write error detection not available yet). Because the write error detection feature is not available yet, you cannot get a valid number of errors by reading the WErr register.
Table 10.  Write control (Offset 16’h0007)
Bit[63:0] Name R/W Default Description
[63:32] rsvd     Reserved
[31] enable R/W 0 0: stop 1: start
[30:8] rsvd     Reserved
[7:0] transfer_size   0 This register configures the burst length per transfer (ideal value for x16 is 8 & x8 is 16). Zero is not a legal value.
Table 11.  Read address mapping table (Offset 16’h0020)The Read address mapping table is 32 locations and 64bit wide each.
Bit[63:0] Name R/W Default Description
[63:0] raDM R/W 0 This register contains the Traffic Checker address mapping table that maps thirty-two 1 MB regions of the Avalon-MM memory space into thirty-two 1 MB regions of the PCIe address space. The module occupies only 32MB of the Avalon-MM address space, and only needs a 25-bit wide address bus, leaving space for other Avalon-MM slaves.
Table 12.  Write address mapping table (Offset 16’h0040)The Write address mapping table is 32 locations and 64bit wide each.
Bit[63:0] Name R/W Default Description
[63:0] WAdm R/W 0 This register contains the Traffic Generator address mapping table that maps thirty-two 1 MB regions of the Avalon-MM memory space into thirty-two 1 MB regions of the PCIe address space. The module occupies only 32MB of the Avalon-MM address space, and only needs a 25-bit wide address bus, leaving space for other Avalon-MM slaves.
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