Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 9/15/2021
Public

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3.3.1. Testbench Overview

Figure 36. Testbench Platform Designer View
Testbench Platform Designer file path: pcie_ed_tb/pcie_ed_tb.qsys

The design example, pcie_ed_inst, is generated with x16. The Intel FPGA BFM, DUT_pcie_tb, can support up to x8 link. The BFM supports the testbench simulation by down-training to x8 link. If you want to simulate x16 link, you can use a third-party BFM.

The testbench uses a Root Port driver module, altpcietb_bfm_rp_gen3_x8.sv ( Path: pcie_ed_tb/ip/pcie_ed_tb/DUT_pcie_tb_ip/altera_pcie_s10_tbed_191/sim ), to exercise the target memory and DMA channel in the Endpoint. This is the module that you can modify to vary the transactions sent to the example Endpoint design or your own design.

For more information about Intel FPGA BFM, refer to Intel Stratix 10 Avalon streaming and SR-IOV Interface for PCI Express Solutions User Guide (Section 9.3 Root Port BFM Overview).

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