Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 9/15/2021
Public

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Document Table of Contents

2.1. Design Example Overview

The Multi Channel DMA for PCI Express IP Design Examples demonstrate a Multi Channel DMA solution for Intel® Stratix® 10 GX/MX devices using the H-Tile PCIe Gen3 hard IP, Intel® Stratix® 10 DX and Intel® Agilex™ devices using the P-Tile PCIe Gen4 Hard IP and soft IP implemented in the FPGA fabric.

You can generate the design example from the Example Designs tab of the Multi Channel DMA for PCI Express IP Parameter Editor. The desired user interface type, either Avalon-ST or Avalon-MM, can be chosen. You can allocate up to 2048 DMA channels (with a maximum of 512 channels per function) when the Avalon-MM Interface type is selected. For the Avalon-ST 4-port Interface, one channel is allocated per port. For the Avalon-ST 1-port interface, you can allocate up to 256 channels in both H-Tile and P-Tile variants. You can also configure the PCIe BAR2 size that is mapped to the Avalon-MM PIO Master port.

Table 2.  Supported Design Example Configurations for H-tile The Hard IP Modes supported are Gen3 x16, 512-bit/Gen3 x8, 256-bit
Design Example User Mode Interface Type Number of Ports Total Channels Supported SR-IOV Support Simulation Synthesis Driver Support
Avalon-MM DMA Multi channel DMA Avalon-MM 1 Up to 2K 2 No Up to 2K channels Up to 2K channels
  • Custom
  • DPDK
  • Kernel Mode
Avalon-MM DMA Multi channel DMA 1 Up to 2K 2 Yes 1 Physical Function and its Virtual Functions Up to 2K channels
  • Custom
  • DPDK
Device-side Packet Loopback Multi channel DMA Avalon-ST 4 4 No 1 channel per port 1 channel per port
  • Custom
  • DPDK
  • Kernel Mode
Packet Generate / Check Multi channel DMA 4 4 No 1 channel per port 1 channel per port
  • Custom
  • DPDK
  • Kernel Mode
PIO using MQDMA Bypass Mode Multi channel DMA 4 N/A No Yes Yes
  • Custom
  • DPDK
  • Kernel Mode
Device-side Packet Loopback Multi channel DMA 1 Up to 256 No Up to 256 channels Up to 256 channels
  • Custom
  • DPDK
  • Kernel Mode
Packet Generate / Check Multi channel DMA 1 Up to 256 No Up to 256 channels Up to 256 channels
  • Custom
  • DPDK
  • Kernel Mode
PIO using MQDMA Bypass Mode Multi channel DMA 1 N/A No Yes Yes
  • Custom
  • DPDK
  • Kernel Mode
Device-side Packet Loopback Multi channel DMA 1 Up to 256 Yes 1 Physical Function and its Virtual Functions Up to 256 channels
  • Custom
  • DPDK
Packet Generate / Check Multi channel DMA 1 Up to 256 Yes 1 Physical Function and its Virtual Functions Up to 256 channels
  • Custom
  • DPDK
PIO using MQDMA Bypass Mode Bursting Master Avalon-MM N/A N/A No Yes Yes
  • Custom
  • DPDK
  • Kernel Mode
Table 3.  Supported Design Example Configurations for P-tile The Hard IP Modes supported are Gen4 x16, 512-bit/Gen4 x8, 256-bit/Gen3 x16, 512-bit/Gen3 x8, 256-bit
Design Example User Mode Interface Type Number of Ports Total Channels Supported SR-IOV Support Simulation Synthesis Driver Support3
Avalon-MM DMA Multi channel DMA Avalon-MM 1 Up to 2K 2 No Up to 2K channels Up to 2K channels
  • Custom
  • DPDK
  • Kernel Mode
Avalon-MM DMA Multi channel DMA 1 Up to 2K 2 Yes Not supported Up to 2K channels
  • Custom
  • DPDK
Device-side Packet Loopback Multi channel DMA Avalon-ST 4 4 No 1 channel per port 1 channel per port
  • Custom
  • DPDK
  • Kernel Mode
Packet Generate / Check Multi channel DMA 4 4 No 1 channel per port 1 channel per port
  • Custom
  • DPDK
  • Kernel Mode
PIO using MQDMA Bypass Mode Multi channel DMA 4 N/A No Yes Yes
  • Custom
  • DPDK
  • Kernel Mode
Device-side Packet Loopback Multi channel DMA 1 Up to 256 No Up to 64 channels Up to 256 channels
  • Custom
  • DPDK
  • Kernel Mode
Packet Generate / Check Multi channel DMA 1 Up to 256 No Up to 64 channels Up to 256 channels
  • Custom
  • DPDK
  • Kernel Mode
PIO using MQDMA Bypass Mode Multi channel DMA 1 N/A No Yes Yes
  • Custom
  • DPDK
  • Kernel Mode
Device-side Packet Loopback Multi channel DMA 1 Up to 256 Yes 4 Not supported Up to 256 channels
  • Custom
  • DPDK
Packet Generate / Check Multi channel DMA 1 Up to 256 Yes 4 Not supported Up to 256 channels
  • Custom
  • DPDK
PIO using MQDMA Bypass Mode Bursting Master Avalon-MM N/A N/A No Yes Yes
  • Custom
  • DPDK
  • Kernel Mode
1 Custom driver is used to generate hardware test results in this document. Every hardware test result is based on the perfq_app command.
2 512 channels per function
3 Custom driver is used to generate hardware test results in this document. Every hardware test result is based on the perfq_app command.
4 Refer to P-tile Avalon Streaming Intel FPGA IP for PCI Express User Guide for supported physical function or virtual function combinations.

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