Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

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ID 683517
Date 9/15/2021
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Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Design Example Detailed Description 3. Design Example Quick Start Guide 4. Multi Channel DMA for FPGA IP Design Example User Guide Archives 5. Document Revision History for the Multi Channel DMA for FPGA IP Design Example User Guide
2. Design Example Detailed Description x
2.1. Design Example Overview 2.2. Hardware and Software Requirements 2.3. PIO Using MCDMA Bypass Mode 2.4. Avalon-ST Packet Generate/Check 2.5. Avalon-ST Device-side Packet Loopback 2.6. Avalon-MM DMA
2.3. PIO Using MCDMA Bypass Mode x
2.3.1. Avalon-ST PIO Using MCDMA Bypass Mode 2.3.2. Avalon-MM PIO Using MCDMA Bypass mode
2.3.1. Avalon-ST PIO Using MCDMA Bypass Mode x
2.3.1.1. Four-Port Avalon-ST PIO Using MCDMA Bypass Mode 2.3.1.2. Single-Port Avalon-ST PIO Using MCDMA Bypass Mode
2.3.1.1. Four-Port Avalon-ST PIO Using MCDMA Bypass Mode x
2.3.1.1.1. Simulation Result 2.3.1.1.2. Hardware Test Result
2.3.2. Avalon-MM PIO Using MCDMA Bypass mode x
2.3.2.1. Simulation Results 2.3.2.2. Hardware Test Results
2.4. Avalon-ST Packet Generate/Check x
2.4.1. Four-Port Avalon-ST Packet Generate/Check 2.4.2. Single-Port Avalon-ST Packet Generate/Check
2.4.1. Four-Port Avalon-ST Packet Generate/Check x
2.4.1.1. Simulation Results 2.4.1.2. Hardware Test Results
2.4.2. Single-Port Avalon-ST Packet Generate/Check x
2.4.2.1. Simulation Waveforms 2.4.2.2. Simulation Log
2.5. Avalon-ST Device-side Packet Loopback x
2.5.1. Simulation Results 2.5.2. Hardware Test Results
2.6. Avalon-MM DMA x
2.6.1. Simulation Results 2.6.2. Hardware Test Results
3. Design Example Quick Start Guide x
3.1. Design Example Directory Structure 3.2. Generating the Example Design using Intel® Quartus® Prime 3.3. Simulating the Design Example 3.4. Compiling the Example Design in Intel® Quartus® Prime 3.5. Running the Design Example Application on a Hardware Setup
3.2. Generating the Example Design using Intel® Quartus® Prime x
3.2.1. Procedure
3.3. Simulating the Design Example x
3.3.1. Testbench Overview 3.3.2. Example Testbench Flow for DMA Test with Avalon-ST Packet Generate/Check Design Example 3.3.3. Run the Simulation Script 3.3.4. View the Results
3.5. Running the Design Example Application on a Hardware Setup x
3.5.1. Program the FPGA 3.5.2. Quick Start Guide
3.5.2. Quick Start Guide x
3.5.2.1. Software Test Setup 3.5.2.2. Driver Support 3.5.2.3. MCDMA Custom Driver 3.5.2.4. MCDMA DPDK Poll Mode Driver 3.5.2.5. MCDMA Kernel Mode Driver
3.5.2.3. MCDMA Custom Driver x
3.5.2.3.1. Prerequisites 3.5.2.3.2. Software Setup 3.5.2.3.3. Run the Reference Example Application
3.5.2.3.1. Prerequisites x
3.5.2.3.1.1. Configuration Changes from BIOS 3.5.2.3.1.2. External Packages 3.5.2.3.1.3. Set the Boot Parameters
3.5.2.3.2. Software Setup x
3.5.2.3.2.1. Installing the Linux Kernel Driver and Enabling VFs 3.5.2.3.2.2. Build and Install User Space Library 3.5.2.3.2.3. Create Guest VM by Using QEMU 3.5.2.3.2.4. Establish Communication Between Host and QEMU
3.5.2.3.3. Run the Reference Example Application x
3.5.2.3.3.1. Meta Data Test 3.5.2.3.3.2. BAM Test 3.5.2.3.3.3. Packet Gen Test
3.5.2.4. MCDMA DPDK Poll Mode Driver x
3.5.2.4.1. Prerequisites 3.5.2.4.2. Install PMD and Test Application 3.5.2.4.3. Run the Reference Example Application
3.5.2.4.1. Prerequisites x
3.5.2.4.1.1. Set the Boot Parameters 3.5.2.4.1.2. Configuration Changes from BIOS 3.5.2.4.1.3. Install and Build Testpmd
3.5.2.4.2. Install PMD and Test Application x
3.5.2.4.2.1. Create VM Environment
3.5.2.5. MCDMA Kernel Mode Driver x
3.5.2.5.1. Prerequisites 3.5.2.5.2. Software Setup 3.5.2.5.3. Examples
3.5.2.5.1. Prerequisites x
3.5.2.5.1.1. Host Configuration 3.5.2.5.1.2. Set the Boot Parameters
3.5.2.5.2. Software Setup x
3.5.2.5.2.1. Build and Install Kernel Driver 3.5.2.5.2.2. Build and Install Libmcmem 3.5.2.5.2.3. Build Testapp 3.5.2.5.2.4. Configure Kernel Driver 3.5.2.5.2.5. Configure Libmcmem 3.5.2.5.2.6. Configure Testapp
1. Terms and Acronyms
2. Design Example Detailed Description
3. Design Example Quick Start Guide
4. Multi Channel DMA for FPGA IP Design Example User Guide Archives
5. Document Revision History for the Multi Channel DMA for FPGA IP Design Example User Guide

3.5.2.2. Driver Support

The table below summarizes the driver support for the MCDMA design example variants. It uses the following acronyms:
  • User Space I/O (UIO): A kernel base module that the PCIe device uses to expose its resources to user space.
  • Virtual Function I/O (VFIO) driver: An IOMMU/device agnostic framework for exposing direct device access to user space in a secure, IOMMU-protected environment.
  • Data Plane Development Kit (DPDK): Consists of libraries to accelerate packet processing workloads running on a wide variety of CPU architectures.
Table 6.  Driver Support for MCDMA Design Examples
  Custom Driver DPDK Driver Kernel Mode Driver
Description Also known as the user mode driver, this driver is created to support both UIO and VFIO base kernel modules. This driver provides custom APIs and can be used without depending on any framework. This DPDK Poll Mode Driver (PMD) uses the DPDK framework. The PMD will expose the device as an ethernet device. It supports both UIO and VFIO base kernel modules. Existing DPDK applications can be integrated with the MCDMA PMD. Kernel Mode Driver (KMD) exposes the MCDMA IP through the char dev interface & using standard char dev file operations performs DMA transfers
Directory/Driver Path <example_design>/software/user <example_design>/software/dpdk <example_design>/software/kernel/
SR-IOV Support Yes Yes No
MCDMA AVMM 1-port DMA Design Example Yes, up to 2K channels Yes, up to 8 channels Yes, up to 2 K channels
MCDMA AVMM 1-port DMA with SR-IOV Design Example Yes, up to 2K channels Yes. up to 2k channels No
Bursting Master AVMM PIO using MQDMA Bypass Mode Design Example Yes Yes. We are supporting now. No
MCDMA AVST 4-port Device-side Packet Loopback Design Example Yes, 1 channel per port Yes, 1 channel per port Yes, 1 channel per port
MCDMA AVST 4-port Packet Generate/Check Design Example Yes, 1 channel per port Yes, 1 channel per port Yes, 1 channel per port
MCDMA AVST 4-Port PIO using MQDMA Bypass Mode Design Example Yes Yes No
MCDMA AVST 1-port Device-side Packet Loopback Design Example Yes Yes, same as custom mode driver Yes
MCDMA AVST 1-port Packet Generate/Check Design Example Yes Yes, same as custom mode driver Yes
MCDMA AVST 1-port PIO using MQDMA Bypass Mode Design Example Yes Yes No
MCDMA AVST 1-port Device-side Packet Loopback with SR-IOV Design Example Yes Yes No
MCDMA AVST 1-port Packet Generate/Check with SR-IOV Design Example Yes Yes No
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