Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 9/15/2021
Public

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Document Table of Contents

1. Terms and Acronyms

Updated for:
Intel® Quartus® Prime Design Suite 21.2
IP Version H.Tile IP version.21.1.0 P.Tile IP version.2.0.0
Table 1.  Acronyms
Term Definition
PCIe* Peripheral Component Interconnect Express ( PCI Express* )
DMA Direct Memory Access
MCDMA Multi Channel Direct Memory Access
PIO Programmed Input/Output
UIO User Space Input/Output
VFIO Virtual Function Input/Output
DPDK Data Plane Development Kit
H2D Host-to-Device
D2H Device-to-Host
H2DDM Host-to-Device Data Mover
D2HDM Device-to-Host Data Mover
QCSR Queue Control and Status register
GCSR General Control and Status Register
IP Intellectual Property
HIP Hard IP
PD Packet Descriptor
QID Queue Identification
TIDX Queue Tail Index (pointer)
HIDX Queue Head Index (pointer)
TLP Transaction Layer Packet
IMMWR Immediate Write Operation
MRRS Maximum Read Request Size
CvP Configuration via Protocol
PBA Pending Bit Array
Avalon® -MM Avalon® Memory-Mapped Interface
Avalon® -ST Avalon® Streaming Interface

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