Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

ID 683517
Date 9/15/2021
Public

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2.5.2. Hardware Test Results

The Custom Driver, DPDK Driver, and Kernel Mode Driver were used to generate the following output:
Figure 26. PIO Test-o option
Figure 27. Performance Test-i option. Note: This hardware test was run with the Intel® Stratix® 10 GX H-tile PCIe Gen3 x16 configuration.
Figure 28. Data Validation Test-i with -v option. Note: This hardware test was run with the Intel® Stratix® 10 GX H-tile PCIe Gen3 x16 configuration.

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