Intel® Stratix® 10 Power Management User Guide

ID 683418
Date 10/31/2023
Document Table of Contents

2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices

The Intel® Stratix® 10 devices require a specific power-up and power-down sequence. This section describes several power management options and discusses proper I/O management during device power-up and power-down. Design your power supply solution to properly control the complete power sequence.

The requirements in this section must be followed to prevent unpredictable current draw to the FPGA device, which can potentially impact the I/O functionality. Intel® Stratix® 10 devices do not support 'Hot-Socketing' except under the conditions stated in the table below. The table below also shows what the unpowered pins can tolerate during power-up and power-down sequences.

The I/O pins are tri-stated with a weak pull-up during power up.

Table 8.  Pin Tolerance—Power-Up/Power-Down'√' is Applicable; '—' is Not Applicable.
Pin Type Power-Up Power-Down
Tristate Drive to GND Drive to VCCIO Driven with < 1.0 Vp-p Tristate Drive to GND Drive to VCCIO Driven with < 1.0 Vp-p
3VIO banks
LVDS I/O banks 10 10
Differential Transceiver pins 11 11
10 The maximum current allowed through any LVDS I/O bank pin when the device is unpowered or during power up/down conditions = 10 mA (refer to "LVDS I/O Pin Guidance for Unpowered FPGA Pins").
11 This applies to Intel® Stratix® 10 L-Tile/H-Tile only (refer to "Transceiver Pin Guidance for Unpowered FPGA Transceiver Pins").