2.3. Power-On Reset Circuitry
The POR circuitry keeps the Intel® Stratix® 10 device in the reset state until the power supply outputs are within the recommended operating range.
A POR event occurs when you power up the Intel® Stratix® 10 device until all power supplies monitored by the POR circuitry reach the recommended operating range within the maximum power supply ramp time, tRAMP . If tRAMP is not met, the Intel® Stratix® 10 device I/O pins and programming registers remain tri-stated, which may cause device configuration to fail.
The Intel® Stratix® 10 POR circuitry uses individual detection circuitry to monitor each of the configuration-related power supplies independently. The POR circuitry is gated by the outputs of all the individual detectors.
POR delay is the time from when the POR trips out to the final reset signal.
The Intel® Stratix® 10 device is held in the POR state until all power supplies have passed their trigger point. After power supplies have passed the trigger point, the SDM will wait for a configurable delay time and then start device configuration.
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