Intel® Stratix® 10 Power Management User Guide

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ID 683418
Date 10/31/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Power Management Overview 2. Intel® Stratix® 10 Power Management Architecture and Features 3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide 4. Intel® Stratix® 10 Power Management User Guide Archives 5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide
2. Intel® Stratix® 10 Power Management Architecture and Features x
2.1. Power Consumption 2.2. Power Reduction Techniques and Features 2.3. Power-On Reset Circuitry 2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices 2.5. Power Supply Design
2.1. Power Consumption x
2.1.1. Dynamic Power Equation
2.2. Power Reduction Techniques and Features x
2.2.1. SmartVID Standard Power Devices 2.2.2. Power-Screened Devices 2.2.3. Temperature Compensation 2.2.4. DSP and M20K Power Gating 2.2.5. Clock Gating 2.2.6. Power Sense Line
2.2.1. SmartVID Standard Power Devices x
2.2.1.1. SmartVID Feature Implementation in Intel® Stratix® 10 Devices 2.2.1.2. SDM Power Manager
2.2.1.2. SDM Power Manager x
2.2.1.2.1. PMBus Master Mode 2.2.1.2.2. PMBus Slave Mode
2.3. Power-On Reset Circuitry x
2.3.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices x
2.4.1. Power-Up Sequence Requirements for Intel® Stratix® 10 Devices 2.4.2. Power-Down Sequence Recommendations and Requirements for Intel® Stratix® 10 Devices
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide x
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started x
3.1.1. Specifying Parameters and Options
3.1.1. Specifying Parameters and Options x
3.1.1.1. Configuration Pin Parameters 3.1.1.2. Power Management and VID Parameters 3.1.1.3. Intel® Stratix® 10 Power Management and VID Interface QSF Constraint Guide
1. Intel® Stratix® 10 Power Management Overview
2. Intel® Stratix® 10 Power Management Architecture and Features
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide
4. Intel® Stratix® 10 Power Management User Guide Archives
5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide

5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide

Document Version Intel® Quartus® Prime Version Changes
2023.10.31 21.1 Updated the SDM Power Manager section.
2022.08.26 21.1 Updated the Multi-Master Mode section.
2022.06.26 21.1 Updated Table: Pin Tolerance—Power-Up/Power-Down.
2022.05.27 21.1 Removed instances of Enpirion from Power Supply Design section and Power Management and VID Parameters table.
2022.04.04 21.1
  • Updated the Clock Gating section.
  • Removed ISL82XX from the slave device type parameters Table: Power Management and VID Parameters.
2021.07.02 21.1 Updated Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram.
2021.03.30 21.1
  • Added reference to the Intel® Stratix® 10 and Intel Agilex® 7 SmartVID Debug Checklist.
  • Added reference to the Intel FPGA Power and Thermal Calculator Standalone and Intel FPGA Power and Thermal Calculator User Guide.
  • Updated the Early Power Estimator (EPE) to Intel® FPGA Power and Thermal Calculator (PTC).
  • Updated the SDM Power Manager section to remove the shutdown stage.
  • Updated Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram.
  • Updated Table: Supported Voltage Output Format for Intel® Stratix® 10 Devices with the –V Power Option.
  • Updated the description of the slave device type and voltage output format parameters in Table: Power Management and VID Parameters.
2020.10.16 20.3
  • Updated the Power-Up Sequence Requirements for Intel® Stratix® 10 Devices section to include information for Group 4 power rails.
  • Updated the Power-Down Sequence Recommendations and Requirements for Intel® Stratix® 10 Devices section to include information for Group 4 power rails.
  • Updated the Intel® Stratix® 10 Power Management and VID Interface QSF Constraint Guide section.
  • Updated the SmartVID value and SmartVID programmed value terms to VID-fused value.
  • Added Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram.
  • Updated Figure: Power-Up Sequence for Intel® Stratix® 10 Devices.
  • Updated Figure: Recommended Power-Down Ramp Specification.
  • Updated Figure: Required Power-Down Ramp Specification.
  • Updated Figure: Required Voltage Differential Specification.
  • Updated Figure: Relaxed Power-Down Duration Specification.
  • Removed note (2) from Figure: External PMBus Master Software Flow.
  • Updated Table: Configuration Pin Parameters to include SDM_IO9 to the Use PWRMGT_ALERT output parameter.
  • Updated Table: Power Management and VID Parameters to include ED8401, EM21XX, and EM22XX to the Slave device type parameter and to update the description of the Enable PAGE command parameter.
2020.04.30 20.1 Added the Supported Voltage Output Format for Intel® Stratix® 10 Devices with the –V Power Option table.
2020.01.23 19.4
  • Added VCCIO3D power rail in Group 3 and VCCIO3C power rail in Group 4 to the Intel® Stratix® 10 GX and SX (L-Tile and H-Tile) column of the Voltage Rails table.
  • Added VCCIO3D and VCCIO3C power supplies to the Power Supplies Monitored and Not Monitored by the Intel® Stratix® 10 POR Circuitry table.
  • Updated the PMBus Slave Mode section.
  • Updated the Power Sequencing Considerations for Intel® Stratix® 10 Devices section.
  • Updated the description for the Use PWRMGT_ALERT output parameter in the Configuration Pin Parameters table.
2019.11.05 19.3 Updated the power rails in Table: Voltage Rails:
  • Removed VCCM_WORD and VCCIO_UIB from the Intel® Stratix® 10 GX and SX (L-Tile and H-Tile) column.
  • Added VCCRT_GXE, VCCRTPLL_GXE, VCCCLK_GXE, and VCCH_GXE in the Intel® Stratix® 10 MX (HBM, H-Tile, and E-Tile) column.
  • Removed VCCL_HPS, VCCPLLDIG_HPS, VCCPLL_HPS, and VCCIO_HPS from the Intel® Stratix® 10 MX (HBM, H-Tile, and E-Tile) column.
  • Removed VCCM_WORD and VCCIO_UIB from the Intel® Stratix® 10 TX (H-Tile and E-Tile) column.
2019.09.19 19.3
  • Added support for Intel® Stratix® 10 DX variant in Table: Voltage Rails.
  • Added the following power rails to Table: Power Supplies Monitored and Not Monitored by the Intel® Stratix® 10 POR Circuitry:
    • VCCFUSE_GXP
    • VCCIO3V
    • VCCH_GXE
    • VCCCLK_GXE
    • VCCRT_GXP
    • VCCH_GXP
    • VCCCLK_GXP
2019.08.23 19.2 Updated the note for VCCBAT in the Power Supplies Monitored and Not Monitored by the POR Circuitry section.
2019.07.01 19.2
  • Added the Multi-Master Mode section.
  • Added ISL82XX device selection in the slave device type parameters in the Power Management and VID Parameters table.
  • Added the Intel® Stratix® 10 Power Management and VID Interface QSF Constraint Guide section.
  • Updated the Temperature Compensation section to include details on the SmartVID value change for the PMBus Master and PMBus Slave modes.
  • Updated the Vp-p value in the Pin Tolerance—Power-Up/Power-Down table.
  • Updated the power rails for Group 1, Group 2, and Group 3 in the Voltage Rails table.
  • Updated the Stage Flow for the External Power Management Controller in the PMBus Slave Mode figure.
  • Updated description in step 6 of the Specifying Parameters and Options section.
  • Updated the description of the slave device type parameter in the Power Management and VID Parameters table.
2018.09.26 18.1
  • Updated the SmartVID details in the Intel® Stratix® 10 Power Management Overview section.
  • Added the power-screened devices feature in the Power Reduction Techniques and Features section.
  • Added the Power-Screened Devices section.
  • Updated the SmartVID regulator requirements in the SmartVID Standard Power Devices section.
  • Updated the Power Sequencing Considerations for Intel® Stratix® 10 Devices section.
  • Updated the Power-Up Sequence Requirements for Intel® Stratix® 10 Devices section to provide more information on the Group 2 and Group3 power rails sharing.
  • Updated the PMBus Master Mode and PMBus Slave Mode figures.
  • Removed support for the Pulse-Width Modulation (PWM) mode.
2018.05.07 18.0
  • Added the MFR_ADC_CONTROL command to the Supported Commands for the PMBus Master Mode table.
  • Updated the SmartVID section to include information for the PWRMGT_SCL and PWRMGT_SDA pins.
  • Updated the Stage Flow for the External Power Management Controller in the PMBus Slave Mode figure.
  • Removed the Monitor Stage for the External Power Management Controller in the PMBus Slave Mode figure.
  • Updated the description of the direct format equation in the PMBus Slave Mode section.
  • Updated the Power Supplies Monitored and Not Monitored by the Intel® Stratix® 10 POR Circuitry table:
    • Added the VCCRT_GXE and VCCRTPLL_GXE rails
    • Removed the VCC_SDM rail
  • Editorial updates.
2018.02.28 17.1
  • Added the Supported Commands for the PMBus Slave Mode table.
  • Added a note about the PWRMGT_ALERT pin for the PMBus Slave mode in the PMBus Mode section.
  • Added a note about the I/O standards supported in the PMBus mode in the PMBus Mode section.
  • Added recommendation to connect to the PWRMGT_ALERT when configuring in the PMBus slave mode in the PMBus Slave Mode section.
  • Added information on the multi-master mode in the PMBus Master Mode section.
  • Added the direct format equation for the PMBus Slave Mode section.
  • Added the Temperature Compensation for SmartVID for Intel® Stratix® 10 Devices figure.
  • Updated the SmartVID section to change the nominal voltage to 0.9V.
  • Updated the SmartVID Regulator Requirements table to update the values for the non-CvP and CvP ramp time.
  • Updated the guidelines for the Power Sense Line section.
  • Updated the Power Sequencing Considerations for Intel® Stratix® 10 Devices section.
  • Updated the value of slave device addresses in the Power Management and VID Parameters table.
  • Updated the steps in the Specifying Parameters and Options section.
  • Updated the SDM Power Manager section to include the initial/shutdown and monitor stages.
  • Removed the Temperature Compensation for SmartVID for Intel® Stratix® 10 Devices table.
Date Version Changes
May 2017 2017.05.08
  • Updated the PowerPlay Early Power Estimator (EPE) to Early Power Estimator.
  • Updated the Power Consumption section to include the standby power.
  • Updated the Power Reduction Techniques section.
  • Updated the SmartVID section to change the nominal voltage to 0.89V.
  • Updated the SmartVID Feature Implementation in Stratix 10 Devices section.
  • Updated the SDM Power Management section.
  • Updated the PMBus Mode section.
  • Updated the PWM Mode section.
  • Updated the Temperature Compensation section.
  • Updated the DSP and M20K Power Gating section.
  • Updated the Clock Gating section.
  • Updated the Power Sense Line section.
  • Updated the Power-On Reset Circuitry section.
  • Updated the Power-Up and Power-Down Sequences section.
  • Updated the Using the SmartVID Feature on VCC and VCCP Rails section.
  • Updated the Power Supply Design section.
  • Updated the Specifying Parameters and Options section.
  • Added the Temperature Compensation for SmartVID for Stratix 10 Devices table.
  • Updated the CvP's ramp time in the SmartVID Regulator Requirements table.
  • Updated the Power Supplies Monitored and Not Monitored by the Stratix 10 POR Circuitry table to include the HPS power supplies.
  • Updated the Power Groups Ramping Sequence table.
  • Updated the Configuration Pin Parameters table.
  • Updated the Power Management and VID Parameters table.
  • Updated the Configuration Pin Parameters table.
  • Updated the Power Management and VID Parameters table.
  • Updated the SDM Power Management Block Diagram figure.
  • Updated the PMBus Master Mode figure.
  • Updated the PMBus Slave Mode figure.
  • Updated the Power-Up and Power-Down Sequences Requirement for Stratix 10 Devices figure.
October 2016 2016.10.31

Initial release.
Level Two Title