2.2.5. Clock Gating
Clock gating can be used to reduce dynamic power consumption. When an application is idle, its clock can be gated temporarily and ungated based on wake-up events. This is done using user logic to enable or disable the global clock (GCLK) and sector clock (SCLK).
You can perform dynamic power reduction by gating the clock signals of any circuitry not used by the design in the Intel® Stratix® 10 devices.
Clock networks can be gated using one of the following methods:
Root Clock Gate
You can dynamically gate each clock network at the root level using the Clock Control Intel FPGA IP core.
Sector Clock Gate
You can dynamically gate each clock network at the clock sector level using the Clock Control Intel FPGA IP core.
I/O PLL Clock Gate
You can dynamically gate each output counter of the Intel® Stratix® 10 I/O PLL's using IOPLL reconfiguration.
Clock gating a large portion of your FPGA design could cause significant current change over a short time period when the gated circuitry is enabled or disabled. The maximum current step resulting from this clock gating should be sized such that it does not create noise exceeding the maximum allowed AC noise specification, as determined by the PDN decoupling design on your PCB. You can control the current step size by dividing a large gated area into smaller sub-regions and staging those regions to enter or exit power gating sequentially.
For more details, refer to the Clock Gating section in the Intel® Stratix® 10 Clocking and PLL User Guide.