Intel® Stratix® 10 Power Management User Guide

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ID 683418
Date 10/31/2023
Public

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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Power Management Overview 2. Intel® Stratix® 10 Power Management Architecture and Features 3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide 4. Intel® Stratix® 10 Power Management User Guide Archives 5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide
2. Intel® Stratix® 10 Power Management Architecture and Features x
2.1. Power Consumption 2.2. Power Reduction Techniques and Features 2.3. Power-On Reset Circuitry 2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices 2.5. Power Supply Design
2.1. Power Consumption x
2.1.1. Dynamic Power Equation
2.2. Power Reduction Techniques and Features x
2.2.1. SmartVID Standard Power Devices 2.2.2. Power-Screened Devices 2.2.3. Temperature Compensation 2.2.4. DSP and M20K Power Gating 2.2.5. Clock Gating 2.2.6. Power Sense Line
2.2.1. SmartVID Standard Power Devices x
2.2.1.1. SmartVID Feature Implementation in Intel® Stratix® 10 Devices 2.2.1.2. SDM Power Manager
2.2.1.2. SDM Power Manager x
2.2.1.2.1. PMBus Master Mode 2.2.1.2.2. PMBus Slave Mode
2.3. Power-On Reset Circuitry x
2.3.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices x
2.4.1. Power-Up Sequence Requirements for Intel® Stratix® 10 Devices 2.4.2. Power-Down Sequence Recommendations and Requirements for Intel® Stratix® 10 Devices
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide x
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started x
3.1.1. Specifying Parameters and Options
3.1.1. Specifying Parameters and Options x
3.1.1.1. Configuration Pin Parameters 3.1.1.2. Power Management and VID Parameters 3.1.1.3. Intel® Stratix® 10 Power Management and VID Interface QSF Constraint Guide
1. Intel® Stratix® 10 Power Management Overview
2. Intel® Stratix® 10 Power Management Architecture and Features
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide
4. Intel® Stratix® 10 Power Management User Guide Archives
5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide

2.3.1. Power Supplies Monitored and Not Monitored by the POR Circuitry

Table 7.  Power Supplies Monitored and Not Monitored by the Intel® Stratix® 10 POR Circuitry
Power Supplies Monitored Power Supplies Not Monitored
  • VCC
  • VCCERAM
  • VCCPT
  • VCCADC
  • VCCIO_SDM
  • VCCBAT
  • VCCL_HPS 7
  • VCCFUSE_GXP 8
  • VCCP
  • VCCR_GXB
  • VCCT_GXB
  • VCCH_GXB
  • VCCIO
  • VCCIO_HPS 7
  • VCCA_PLL
  • VCCFUSEWR_SDM
  • VCCPLLDIG_SDM
  • VCCPLLDIG_HPS 7
  • VCCPLL_HPS 7
  • VCCPLL_SDM
  • VCCM_WORD
  • VCCIO_UIB
  • VCCRT_GXE
  • VCCRTPLL_GXE
  • VCCIO3V
  • VCCH_GXE
  • VCCCLK_GXE
  • VCCRT_GXP
  • VCCH_GXP
  • VCCCLK_GXP
  • VCCIO3D 9
  • VCCIO3C 9
Note: Intel® recommends you to connect VCCBAT to a 1.8V power supply if you do not use the design security feature in Intel® Stratix® 10 devices.
7 These are only supported by system-on-a-chip (SoC) FPGA.
8 This power rail will not gate SDM power up, but it will gate FPGA configuration.
9 Applies to the 1SG040 and 1SX040 devices only.
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