Intel® Stratix® 10 Power Management User Guide

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ID 683418
Date 10/31/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Power Management Overview 2. Intel® Stratix® 10 Power Management Architecture and Features 3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide 4. Intel® Stratix® 10 Power Management User Guide Archives 5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide
2. Intel® Stratix® 10 Power Management Architecture and Features x
2.1. Power Consumption 2.2. Power Reduction Techniques and Features 2.3. Power-On Reset Circuitry 2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices 2.5. Power Supply Design
2.1. Power Consumption x
2.1.1. Dynamic Power Equation
2.2. Power Reduction Techniques and Features x
2.2.1. SmartVID Standard Power Devices 2.2.2. Power-Screened Devices 2.2.3. Temperature Compensation 2.2.4. DSP and M20K Power Gating 2.2.5. Clock Gating 2.2.6. Power Sense Line
2.2.1. SmartVID Standard Power Devices x
2.2.1.1. SmartVID Feature Implementation in Intel® Stratix® 10 Devices 2.2.1.2. SDM Power Manager
2.2.1.2. SDM Power Manager x
2.2.1.2.1. PMBus Master Mode 2.2.1.2.2. PMBus Slave Mode
2.3. Power-On Reset Circuitry x
2.3.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices x
2.4.1. Power-Up Sequence Requirements for Intel® Stratix® 10 Devices 2.4.2. Power-Down Sequence Recommendations and Requirements for Intel® Stratix® 10 Devices
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide x
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started x
3.1.1. Specifying Parameters and Options
3.1.1. Specifying Parameters and Options x
3.1.1.1. Configuration Pin Parameters 3.1.1.2. Power Management and VID Parameters 3.1.1.3. Intel® Stratix® 10 Power Management and VID Interface QSF Constraint Guide
1. Intel® Stratix® 10 Power Management Overview
2. Intel® Stratix® 10 Power Management Architecture and Features
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide
4. Intel® Stratix® 10 Power Management User Guide Archives
5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide

2.2.1.2.2. PMBus Slave Mode

Intel® Stratix® 10 devices can also be configured in the PMBus slave mode with an external power management controller acting as the PMBus master. When you configure the Intel® Stratix® 10 device in the PMBus slave mode, you must connect an additional PWRMGT_ALERT pin while connecting the existing PWRMGT_SCL and PWRMGT_SDA pins.

Note: The PMBus mode only supports the 1.8-V I/O standard.

The external PMBus master must poll the state of the PWRMGT_ALERT pin periodically, at an interval not longer than 100ms. When the PWRMGT_ALERT pin is asserted, the external master uses the Alert Response Address (ARA) flow to de-assert the ALERT signal and responds based on the STATUS_BYTE. The external master must also issue the VOUT_COMMAND every 200ms or less to check for a possible change in the target voltage due to temperature compensation.

Note: The same VOUT_COMMAND is used for reading the target voltage from the SDM or setting the voltage regulator to the new target voltage. When the Intel® Stratix® 10 device operates in the PMBus slave mode, the external master sends the VOUT_COMMAND to the SDM to get the target voltage required by the SDM. The external master then sends a VOUT_COMMAND to the voltage regulator to set its voltage.
Figure 4. PMBus Slave Mode
Table 4.  Supported Commands for the PMBus Slave Mode
Command Name Command Code Default PMBus Transaction Type Number of Bytes
CLEAR_FAULTS 03h — Send byte 0
VOUT_MODE 20h 40h Read byte 1
VOUT_COMMAND 21h — Read word 2
STATUS_BYTE 78h 00h Read byte 1
Figure 5. External PMBus Master Software Flow
Table 5.  Stage Flow for the External PMBus Master when the ALERT Signal is Asserted and STATUS_BYTE=0
Sequence SDM PMBus Master Notes
1 Asserts the ALERT signal — —
2 — Detects the ALERT signal —
3 — Initiates the ARA flow —
4 Responds to the ARA flow and provides its address — Only the device which has asserted the ALERT signal in step 1 responds to the ARA flow by providing its address.
5 De-asserts the ALERT signal — The ALERT signal is only de-asserted after the SDM responds with its address in the ARA flow.
6 — Reads the STATUS_BYTE —
7 Returns STATUS_BYTE=0 — Indicates the FPGA voltage requires an update.
8 — Sends CLEAR_FAULTS —
9 — Sends VOUT_COMMAND The VOUT_COMMAND must be received by the SDM within 200ms after the ALERT signal is asserted. Failure to meet this requirement will cause configuration error. 5
10 Receives the VOUT_COMMAND, responds with the target voltage — Calculated based on the temperature, the VID fuse and the coefficient for the direct format (you need to specify this input).
11 — Sets the voltage regulator to the target voltage in step size not greater than 10mV/10ms step —
Table 6.  Stage Flow for the External PMBus Master when the ALERT Signal is Asserted and STATUS_BYTE is not equal to 0
Sequence SDM PMBus Master Notes
1 Asserts the ALERT signal — The SDM detects fault and asserts the ALERT signal. 6
2 — Detects the ALERT signal —
3 — Initiates the ARA flow —
4 Responds to the ARA flow and provides its address — Only the device which has asserted the ALERT signal in step 1 responds to the ARA flow by providing its address.
5 De-asserts the ALERT signal — The ALERT signal is only de-asserted after the SDM responds with its address in the ARA flow.
6 — Reads the STATUS_BYTE —
7 Returns the STATUS_BYTE when not equal to 0 — Indicates that other fault has occurred
8 — Sends CLEAR_FAULTS To reset the STATUS_BYTE.
9 — Reads the STATUS_BYTE To confirm that STATUS_BYTE=0
10 — External master to handle the faults —
Figure 6. Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram

The Intel® Stratix® 10 device in the PMBus slave mode will be sending the VOUT_COMMAND value in the direct format only. To read the actual voltage value, use the following equation to convert the VOUT_COMMAND value from the Intel® Stratix® 10 device.

Figure 7. Direct Format Equation

The equation shows how to convert the direct format value where:

  • X, is the calculated, real value units in mV;
  • m, is the slope coefficient, a 2-byte two's complement integer;
  • Y, is the 2-byte two's complement integer received from the Intel® Stratix® 10 device;
  • b, is the offset, a 2-byte two's complement integer;
  • R, is the exponent, a 1-byte two's complement integer

The following example shows how an external power management controller retrieves values from the Intel® Stratix® 10 device. Coefficients used in the VOUT_COMMAND are as follows:

  • m = 1
  • b = 0
  • R = 0

If the external power management controller retrieved a value of 0384h, it is equivalent to the following:

X = (1/1) x (0384h x 10-0 - 0) = 900 mV = 0.90 V

5 When there is an error triggered by the SDM because it did not receive the VOUT_COMMAND within the specified time, you must power cycle the device to recover from the error. If you do not power cycle the device to recover from the error, you will not be able to configure the device successfully.
6

The following faults can raise the ALERT signal:

  • PMBUS_ERR_RD_TOO_MANY_BYTES (Error with the length of the PMBus/I2C message length)
  • PMBUS_ERR_WR_TOO_MANY_BYTES (Error with the length of the PMBus/I2C message length)
  • PMBUS_ERR_UNSUPPORTED_CMD (VOUT_COMMAND, VOUT_MODE, READ_STATUS, and CLEAR_FAULTS are the only supported commands in the PMBUS Slave Mode)
  • PMBUS_ERR_READ_FLAG (Received duplicate command before being able to respond to the first command)
  • PMBUS_ERR_INVALID_DATA (Invalid or malformed PMBus/I2C message)

If any of the above errors are detected, the ALERT signal is raised and bit 1 of the status register is set.

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