126.96.36.199.1. PMBus Master Mode
In the PMBus master mode, during the initial stage, the SDM Power Manager powers up the VCC and VCCP to the voltage level based on the VID-fused value and the device temperature before it starts to configure the FPGA. After entering the user mode (in the monitor stage), the SDM Power Manager monitors temperature changes and decides if the VCC and VCCP output voltage values need to be updated. If voltages require updating, the SDM Power Manager identifies the voltage value based on the fuse values and the current temperature and sends the desired voltage value to the voltage regulators through the PMBus (PWRMGT_SCL and PWRMGT_SDA).
|Command Name||Command Code||PMBus Transaction Type||Number of Bytes|
|PAGE 2||00h||Write byte||1|
|VOUT_MODE 3||20h||Read byte||1|
|MFR_ADC_CONTROL 4||D8h||Write byte||1|
The PMBus master mode supports the multi-master mode.
When multiple devices start to communicate at the same time, the device writing the most zeros to the bus or the slowest device wins the arbitration. The other devices immediately discontinue any operation on the bus. When there is an on-going bus communication, all devices must detect the communication and not interrupt it. The devices must wait for a stop condition to appear before starting communication to the bus. Once the stop condition is received on the bus, the next device that wins arbitration sends a start condition by pulling the PWRMGT_SDA low to re-initialize the bus communication.
In this mode, all master devices must be multi masters in a multi-master system. Single-master systems may not understand the arbitration and the busy detection mechanisms can cause unpredictable results.
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