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1. Intel® Stratix® 10 Power Management Overview
2. Intel® Stratix® 10 Power Management Architecture and Features
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide
4. Intel® Stratix® 10 Power Management User Guide Archives
5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide
2.2.4. DSP and M20K Power Gating
Power gating of the DSP blocks and M20K memory blocks is enabled via the configuration RAM (CRAM) bits. Intel® Stratix® 10 devices support power gating for both DSP blocks and M20K memory blocks. By default, the Intel® Quartus® Prime software automatically configures unused DSP blocks and M20K memory blocks to be power gated.