Stratix V Avalon-MM Interface for PCIe Solutions: User Guide
ID
683411
Date
5/21/2017
Public
1. Datasheet
2. Getting Started with the Avalon-MM Design Example
3. Parameter Settings
4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer
5. Registers
6. Interrupts for Endpoints
7. Error Handling
A. PCI Express Protocol Stack
8. Transceiver PHY IP Reconfiguration
9. Throughput Optimization
10. Design Implementation
11. Additional Features
12. Debugging
B. Frequently Asked Questions for PCI Express
C. Lane Initialization and Reversal
D. Document Revision History
2.1. Running Qsys
2.2. Generating the Example Design
2.3. Understanding Simulation Log File Generation
2.4. Running a Gate-Level Simulation
2.5. Simulating the Single DWord Design
2.6. Generating Synthesis Files
2.7. Creating a Quartus® Prime Project
2.8. Compiling the Design
2.9. Programming a Device
2.10. Understanding Channel Placement Guidelines
4.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals
4.2. Bursting and Non-Bursting Avalon® -MM Module Signals
4.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals
4.4. Clock Signals
4.5. Reset
4.6. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled
4.7. Hard IP Status Signals
4.8. Physical Layer Interface Signals
5.1. Correspondence between Configuration Space Registers and the PCIe Specification
5.2. Type 0 Configuration Space Registers
5.3. Type 1 Configuration Space Registers
5.4. PCI Express Capability Structures
5.5. Intel-Defined VSEC Registers
5.6. CvP Registers
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions
5.8. Programming Model for Avalon-MM Root Port
5.9. Uncorrectable Internal Error Mask Register
5.10. Uncorrectable Internal Error Status Register
5.11. Correctable Internal Error Mask Register
5.12. Correctable Internal Error Status Register
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers
5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers
5.7.1.3. PCI Express Mailbox Registers
5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table
5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
5.7.1.6. Avalon-MM Mailbox Registers
5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
A.4.1. Avalon‑MM Bridge TLPs
A.4.2. Avalon-MM-to-PCI Express Write Requests
A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests
A.4.4. PCI Express-to-Avalon-MM Read Completions
A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests
A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests
A.4.7. Avalon-MM-to-PCI Express Read Completions
A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge
A.4.9. Minimizing BAR Sizes and the PCIe Address Space
A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
11.1. Configuration over Protocol (CvP)
The Hard IP for PCI Express architecture has an option to configure the FPGA and initialize the PCI Express link. In prior devices, a single Program Object File (.pof) programmed the I/O ring and FPGA fabric before the PCIe link training and enumeration began. The .pof file is divided into two parts:
- The I/O bitstream contains the data to program the I/O ring, the Hard IP for PCI Express, and other elements that are considered part of the periphery image.
- The core bitstream contains the data to program the FPGA fabric.
When you select the CvP design flow, the I/O ring and PCI Express link are programmed first, allowing the PCI Express link to reach the L0 state and begin operation independently, before the rest of the core is programmed. After the PCI Express link is established, it can be used to program the rest of the device. The following figure shows the blocks that implement CvP.
Figure 45. CvP in Stratix V Devices
CvP has the following advantages:
- Provides a simpler software model for configuration. A smart host can use the PCIe protocol and the application topology to initialize and update the FPGA fabric.
- Enables dynamic core updates without requiring a system power down.
- Improves security for the proprietary core bitstream.
- Reduces system costs by reducing the size of the flash device to store the .pof.
- Facilitates hardware acceleration.
- May reduce system size because a single CvP link can be used to configure multiple FPGAs.
Data Rate and Application Interface Width | Support |
---|---|
Gen1 128-bit interface to Application Layer | Supported |
Gen2 128-bit interface to Application Layer | Contact your Intel sales representative |
Gen3 128- or 256-bit interface to the Application Layer | Not supported |
Note: You cannot use dynamic transceiver reconfiguration for the transceiver channels in the CvP-enabled Hard IP when CvP is enabled.
Note: The Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide is now available.