1.1. Software and Hardware Requirements
1.2. Download and Install the Tutorial Design Files
1.3. Open the Tutorial Project
1.4. Creating Qsys Systems
1.5. Assemble a Hierarchical System
1.6. Viewing the Memory Tester System in Qsys
1.7. Compiling and Downloading Software to a Development Board
1.8. Debugging Your Design
1.9. Verifying Hardware in System Console
1.10. Simulating Custom Components
1.11. View a Diagram of the Completed System
1.4.1.1. Create a New Qsys System and Set up the Clock Source
1.4.1.2. Add a Pipeline Bridge
1.4.1.3. Add a Custom Pattern Generator
1.4.1.4. Add a PRBS Pattern Generator
1.4.1.5. Add a Two-to-One Streaming Multiplexer
1.4.1.6. Verify the Memory Address Map
1.4.1.7. Connect the Reset Signals
1.4.1.8. Save the System
1.4.2.1. Create a New Qsys System and Set Up the Clock Soource
1.4.2.2. Add a Pipeline Bridge
1.4.2.3. Add a Custom Pattern Checker
1.4.2.4. Add the PRBS Pattern Checker
1.4.2.5. Add a One-to-Two Streaming Demultiplexer
1.4.2.6. Verify the Memory Address Map
1.4.2.7. Connect the Reset Signals
1.4.2.8. Save the System
1.10.1. Generate a Testbench System in Qsys
The custom pattern generator generates high-speed streaming data for testing memory devices. The soft-programmable custom pattern generator can generate multiple test patterns, and is programmed with the pattern data and pattern length. When the end of the pattern is reached, the custom pattern generator cycles back to the first element of the pattern.
If you do not want to use the Qsys-generated testbench system, you can create your own Qsys testbench system by adding the Avalon Verification Suite Bus Functional Models (BFMs) or your own models for simulation. You can also generate a Qsys simulation model for the design or Qsys system under test, and use your own custom HDL testbench to provide the simulation stimulus.