Qsys System Design Tutorial

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ID 683378
Date 5/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Qsys System Design Tutorial
1. Qsys System Design Tutorial x
1.1. Software and Hardware Requirements 1.2. Download and Install the Tutorial Design Files 1.3. Open the Tutorial Project 1.4. Creating Qsys Systems 1.5. Assemble a Hierarchical System 1.6. Viewing the Memory Tester System in Qsys 1.7. Compiling and Downloading Software to a Development Board 1.8. Debugging Your Design 1.9. Verifying Hardware in System Console 1.10. Simulating Custom Components 1.11. View a Diagram of the Completed System
1.4. Creating Qsys Systems x
1.4.1. Create a Data Pattern Generator Qsys System 1.4.2. Create a Data Pattern Checker Qsys System
1.4.1. Create a Data Pattern Generator Qsys System x
1.4.1.1. Create a New Qsys System and Set up the Clock Source 1.4.1.2. Add a Pipeline Bridge 1.4.1.3. Add a Custom Pattern Generator 1.4.1.4. Add a PRBS Pattern Generator 1.4.1.5. Add a Two-to-One Streaming Multiplexer 1.4.1.6. Verify the Memory Address Map 1.4.1.7. Connect the Reset Signals 1.4.1.8. Save the System
1.4.2. Create a Data Pattern Checker Qsys System x
1.4.2.1. Create a New Qsys System and Set Up the Clock Soource 1.4.2.2. Add a Pipeline Bridge 1.4.2.3. Add a Custom Pattern Checker 1.4.2.4. Add the PRBS Pattern Checker 1.4.2.5. Add a One-to-Two Streaming Demultiplexer 1.4.2.6. Verify the Memory Address Map 1.4.2.7. Connect the Reset Signals 1.4.2.8. Save the System
1.5. Assemble a Hierarchical System x
1.5.1. Create the Hierarchical Memory Tester System 1.5.2. Complete the Top-Level System
1.5.1. Create the Hierarchical Memory Tester System x
1.5.1.1. Add the Pattern Generator 1.5.1.2. Add the Pattern Checker 1.5.1.3. Add Memory Master Components 1.5.1.4. Connect the Reset Signals 1.5.1.5. Verify the Memory Address Map 1.5.1.6. Save the System
1.5.1.3. Add Memory Master Components x
1.5.1.3.1. Add a Pattern Writer Component 1.5.1.3.2. Add a Pattern Reader Component 1.5.1.3.3. Add a RAM Test Controller
1.9. Verifying Hardware in System Console x
1.9.1. Open the Tutorial Project 1.9.2. Add the JTAG-to-Avalon Master Bridge 1.9.3. Debug with System Console
1.10. Simulating Custom Components x
1.10.1. Generate a Testbench System in Qsys 1.10.2. Run Simulation In the ModelSim-Altera Software
1.10.1. Generate a Testbench System in Qsys x
1.10.1.1. Create a New Qsys System for the Design Under Test 1.10.1.2. Export Design Under Test 1.10.1.3. Generate a Testbench System 1.10.1.4. Generate Testbench System's Simulation Models
1.10.2. Run Simulation In the ModelSim-Altera Software x
1.10.2.1. Set Up the Simulation Environment 1.10.2.2. Run the Simulation
1. Qsys System Design Tutorial

1.7. Compiling and Downloading Software to a Development Board

Altera recommends that you download the memory tester system to a development board to complete the design process and test the memory interface of the board. If you do not have a development board you can follow the steps provided in the accompanying readme.txt file to learn more details about porting designs to FPGA devices or boards.

The Altera-provided software tests the memory using various test parameters and patterns, and is scripted for compilation and download to the board.

  1. To download the top-level system to a development board, in Qsys, click Generate > Generate.
  2. Select the language for Create HDL design files for synthesis, and turn off the option to create a Block Symbol File (.bsf).
  3. Click Generate. Qsys generates HDL files for the system and the Quartus II IP File (.qip) that provides the list of required HDL files for the Quartus II compilation.
  4. When Qsys completes the generation, click Close.
  5. In the Quartus II software, on the Project menu, click Add/Remove Files in Project and verify that the newly-generated .qip file, top_system.qip, and the timing constraints file, my_constraints.sdc appear in the Files list.
  6. Click Processing > Start Compilation. When compilation completes, click OK.
  7. Connect the development board to a supported programming cable.
  8. Click Tools > Nios II Command Shell [gcc4].
  9. Type the following command to emulate your local c:/ drive for your Windows environment: cd /cygdrive/c/.
  10. Navigate to the quartus_ii_projects_for_boards\<development_board>\software directory.
  11. Type the following command at the Nios II command Shell: ./batch_script.sh.
    The batch script compiles the Nios II software and downloads the SRAM Object File (.sof) programming file to the FPGA.

The terminal window shows messages indicating the progress. If you see error messages related to the JTAG chain, check your programming cable installation and board setup to ensure that it is set up correctly.

After the script configures the FPGA, it downloads the compiled Nios II software to the board and establishes a terminal connection with the board. The test software performs test sweeps on the SDRAM by varying the following parameters:

  • Pattern type
  • Memory block size
  • Memory block trail distance (number of blocks by which the pattern reader trails the pattern writer)
  • Memory span tested

Ensure that you have only one set of generated system files in the project directory, otherwise the batch script to program the device fails with an error from the software build tools.

The memory throughput values appear in the command terminal as the memory is tested. These values are reported in hexadecimal and represent the number of clock cycles required to test the entire SDRAM address span. The output is restricted to hexadecimal due to a small software library that prints the characters to the terminal. Because the memory tester system writes to the memory and then reads it back, the number of bytes it accesses and reports in the transcript window is double the memory span. This number varies depending on the span of memory being tested for your memory device. Knowing the data width of the memory interface, the number of bytes transferred, and the number of clock cycles for the transfer, you can determine the memory access efficiency.

The SDRAM controller in the top-level Qsys system has a 32-bit local interface width, therefore memory data width in bytes is 4 bytes for the tutorial design. 

Efficiency = 100 × total bytes transferred/(memory data width in bytes × total clock cycles)

The memory test runs until the design finishes testing the complete memory. To end the test early, type Ctrl+C in the command window. To calculate the efficiency for the last throughput numbers in, convert the hexadecimal numbers to decimal, as follows:

  • 0x4000000 bytes transferred is 0d67108864 total bytes transferred
  • 0x107d856 clock cycles is 0d17291350 total clock cycles

Therefore, the efficiency for this example is: 

100 × 67108864 / (4 × 17291350) = 97.0%
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