Qsys System Design Tutorial

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ID 683378
Date 5/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Qsys System Design Tutorial
1. Qsys System Design Tutorial x
1.1. Software and Hardware Requirements 1.2. Download and Install the Tutorial Design Files 1.3. Open the Tutorial Project 1.4. Creating Qsys Systems 1.5. Assemble a Hierarchical System 1.6. Viewing the Memory Tester System in Qsys 1.7. Compiling and Downloading Software to a Development Board 1.8. Debugging Your Design 1.9. Verifying Hardware in System Console 1.10. Simulating Custom Components 1.11. View a Diagram of the Completed System
1.4. Creating Qsys Systems x
1.4.1. Create a Data Pattern Generator Qsys System 1.4.2. Create a Data Pattern Checker Qsys System
1.4.1. Create a Data Pattern Generator Qsys System x
1.4.1.1. Create a New Qsys System and Set up the Clock Source 1.4.1.2. Add a Pipeline Bridge 1.4.1.3. Add a Custom Pattern Generator 1.4.1.4. Add a PRBS Pattern Generator 1.4.1.5. Add a Two-to-One Streaming Multiplexer 1.4.1.6. Verify the Memory Address Map 1.4.1.7. Connect the Reset Signals 1.4.1.8. Save the System
1.4.2. Create a Data Pattern Checker Qsys System x
1.4.2.1. Create a New Qsys System and Set Up the Clock Soource 1.4.2.2. Add a Pipeline Bridge 1.4.2.3. Add a Custom Pattern Checker 1.4.2.4. Add the PRBS Pattern Checker 1.4.2.5. Add a One-to-Two Streaming Demultiplexer 1.4.2.6. Verify the Memory Address Map 1.4.2.7. Connect the Reset Signals 1.4.2.8. Save the System
1.5. Assemble a Hierarchical System x
1.5.1. Create the Hierarchical Memory Tester System 1.5.2. Complete the Top-Level System
1.5.1. Create the Hierarchical Memory Tester System x
1.5.1.1. Add the Pattern Generator 1.5.1.2. Add the Pattern Checker 1.5.1.3. Add Memory Master Components 1.5.1.4. Connect the Reset Signals 1.5.1.5. Verify the Memory Address Map 1.5.1.6. Save the System
1.5.1.3. Add Memory Master Components x
1.5.1.3.1. Add a Pattern Writer Component 1.5.1.3.2. Add a Pattern Reader Component 1.5.1.3.3. Add a RAM Test Controller
1.9. Verifying Hardware in System Console x
1.9.1. Open the Tutorial Project 1.9.2. Add the JTAG-to-Avalon Master Bridge 1.9.3. Debug with System Console
1.10. Simulating Custom Components x
1.10.1. Generate a Testbench System in Qsys 1.10.2. Run Simulation In the ModelSim-Altera Software
1.10.1. Generate a Testbench System in Qsys x
1.10.1.1. Create a New Qsys System for the Design Under Test 1.10.1.2. Export Design Under Test 1.10.1.3. Generate a Testbench System 1.10.1.4. Generate Testbench System's Simulation Models
1.10.2. Run Simulation In the ModelSim-Altera Software x
1.10.2.1. Set Up the Simulation Environment 1.10.2.2. Run the Simulation
1. Qsys System Design Tutorial

1.5.2. Complete the Top-Level System

  1. In Qsys, open the top_system.qsys file from the tt_qsys_design\quartus_ii_projects_for_boards\<development_board> directory.
    The top-level system is set up for your development board, with an external clock source, a processor system, and an SDRAM controller. You can view the clocks in top-level system on the Clock Settings tab, and the partially-completed system connections on the System Contents tab.
  2. In the IP Catalog, double-click memory_tester_system from the System group.
  3. Click Finish to accept the default parameters, and to add the memory tester system to the top-level system.
  4. Rename the system to memory_tester_subsystem.
  5. On the System Contents tab, use the arrows to move the memory_tester_subsystem up between the cpu_subsystem and the sdram.
    Since the cpu_subsystem controls the memory_tester_subsystem, and the memory_tester_subsystem controls the sdram, this positioning allows you to more easily visualize system performance.
  6. Set the memory_tester_subsystem clk to either the sdram_sysclk (for ALTMEMPHY-based designs), or sdram_afi_clk (for UniPHY-based designs).
    Some boards have an FPGA and SDRAM device that use either the Altera DDR or DDR2 SDRAM Controller with ALTMEMPHY; others use the Altera DDR3 SDRAM controller with UniPHY.
  7. Connect the memory_tester_subsystem reset interface to the ext_clk clk_reset interface.
  8. Connect the memory_tester_subsystem reset interface to the cpu_subsystem cpu_jtag_debug_reset interface.
    This design exports the Nios II processor JTAG debug reset output interface, jtag_debug_module_reset, from the cpu_subsystem with the interface name cpu_ jtag_debug_reset. The design must connect this Nios II reset output to any component reset inputs that require resetting by the Nios II processor code or JTAG interface, and also to the Nios II processor's reset input interface. The cpu_subsystem cpu_reset interface connects to the Nios II processor's reset input interface. The top_level.qsys file connects the cpu_jtag_debug_reset interface to the cpu_reset interface.
  9. Connect the memory_tester_subsystem write_master and read_master interfaces to either the sdram s1 interface (for ALTMEMPHY-based designs), or sdram avl interface (for UniPHY-based designs).
  10. Connect the memory_tester_subsystem slave interface to the cpu_subsystem master interface.
  11. Maintain the base addresses of 0x0 for the memory_tester_subsystem slave interface, and for either the sdram s1 interface (for ALTMEMPHY-based designs), or sdram avl interface (for UniPHY-based designs).

The two slave interfaces can use the same address map range because different masters control them. The cpu_subsystem master interface controls the memory_tester_subsystem, and the memory_tester_subsystem write_master and read_master interfaces control the sdram interface.

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