1.1. Software and Hardware Requirements
1.2. Download and Install the Tutorial Design Files
1.3. Open the Tutorial Project
1.4. Creating Qsys Systems
1.5. Assemble a Hierarchical System
1.6. Viewing the Memory Tester System in Qsys
1.7. Compiling and Downloading Software to a Development Board
1.8. Debugging Your Design
1.9. Verifying Hardware in System Console
1.10. Simulating Custom Components
1.11. View a Diagram of the Completed System
1.4.1.1. Create a New Qsys System and Set up the Clock Source
1.4.1.2. Add a Pipeline Bridge
1.4.1.3. Add a Custom Pattern Generator
1.4.1.4. Add a PRBS Pattern Generator
1.4.1.5. Add a Two-to-One Streaming Multiplexer
1.4.1.6. Verify the Memory Address Map
1.4.1.7. Connect the Reset Signals
1.4.1.8. Save the System
1.4.2.1. Create a New Qsys System and Set Up the Clock Soource
1.4.2.2. Add a Pipeline Bridge
1.4.2.3. Add a Custom Pattern Checker
1.4.2.4. Add the PRBS Pattern Checker
1.4.2.5. Add a One-to-Two Streaming Demultiplexer
1.4.2.6. Verify the Memory Address Map
1.4.2.7. Connect the Reset Signals
1.4.2.8. Save the System
1.5.1.2. Add the Pattern Checker
The pattern checker system validates data that arrives via an Avalon-ST sink interface. You control the system by accessing the memory locations allocated to each component within the subsystem. The system connects all of the slave ports to a pipeline bridge, which it then exposes outside of the system.
The pattern checker system contains the following components:
- Pipeline bridge
- Custom pattern checker
- PRBS pattern checker
- One-to-two demultiplexer
- In the IP Catalog, double-click pattern_checker_system from the System group.
- In the parameter editor, click Finish to accept the default settings.
- Rename the instance to pattern_checker_subsystem.
- Set the pattern_checker_subsystem clk to clk_0.
- Connect the pattern_checker_subsystem slave interface to the mm_bridge m0 interface.
- Connect the pattern_checker_subsystem reset interface to the clk_0 clk_reset interface.