Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 12/08/2023
Document Table of Contents

2.2.1. Reset Strategies

This section recommends techniques to achieve maximum performance when using reset signals.
To hold your design in reset until configuration is complete, you must implement the Reset Release Intel® FPGA IP, or the INIT_DONE signal (routed back in through a pin). Refer to the Intel Agilex® 7 Configuration User Guide or Intel® Stratix® 10 Configuration User Guide for more details on reset for your device.

For the best performance, avoid resets (asynchronous and synchronous), except when necessary. Because Hyper-Registers do not have asynchronous resets, the Compiler cannot retime any register with an asynchronous reset into a Hyper-Register location.

Using a synchronous instead of asynchronous reset allows retiming of a register. Refer to the Synchronous Resets and Limitations section for more detailed information about retiming behavior for registers with synchronous resets. Some registers in your design require synchronous or asynchronous resets, but you must minimize the number for best performance.