Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 12/08/2023
Document Table of Contents Ternary Adders

Implementing ternary adders can increase resource usage in Intel® Hyperflex™ architecture FPGAs. However, unless your design heavily relies on ternary adder structure, additional resource usage may not be noticeable at the top design level. However, a review of the design level at which you add a ternary adder structure can show an increase in LUT count. In addition, the amount of resource increase directly correlates to the size of the adder. Small width adders (size < 16 bits) do not cause much resource difference. However, increasing the size of the adder increases the resource count differential, in comparison with older FPGA technology.

Ternary Adder RTL Code

module ternary_adder (CLK, A, B, C, OUT);
	parameter WIDTH = 16;
	input [WIDTH-1:0] A, B, C;
	input 			  CLK;
	output [WIDTH-1:0] OUT;

	wire [WIDTH-1:0]    sum1;	
	reg [WIDTH-1:0]   sumreg1;

   	// 3-bit additions
	assign 			  sum1 = A + B + C;		
	assign 			  OUT = sumreg1;

	// Registers
	always @ (posedge CLK)
			sumreg1 <= sum1;

This increase in device resource use occurs because the Intel® Hyperflex™ architecture ALM does not have a shared arithmetic mode that previous FPGA technologies have. The ALM in shared arithmetic mode can implement a three-input add in the ALM. By contrast, the Intel® Hyperflex™ architecture ALM can implement only a two-input add in the ALM.

Figure 78. RTL View of Intel® Arria® 10 versus Intel® Hyperflex™ Architecture FPGAs to add 2 LSBs from a three 8-bit input adder

In shared arithmetic mode, the Intel® Arria® 10 ALM allows a three-input adder to use three adaptive LUT (ALUT) inputs: CIN, SHAREIN, COUT, SUMOUT, and SHAREOUT. The absence of the shared arithmetic mode restricts ALM use with only two ALUT inputs: CIN, COUT and SUMOUT. The figure below shows the resulting implementation of a ternary adder on both Intel® Arria® 10 and Intel® Hyperflex™ architecture FPGAs.

Figure 79.  Intel® Arria® 10: ALMs used to add 2 LSBs from a three 8-bit input adder
Figure 80.  Intel® Hyperflex™ Architecture FPGAs: ALMs used to add 2 LSBs from a three 8-bit input adder