Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 12/08/2023
Document Table of Contents

2. Intel® Hyperflex™ Architecture RTL Design Guidelines

This chapter describes RTL design techniques to achieve the highest clock rates possible in Intel® Hyperflex™ architecture FPGAs. Intel® Hyperflex™ architecture FPGAs support maximum clock rates significantly higher than previous FPGA generations.
Note: Avoiding RTL design rule violations improves the reliability, timing performance, and logic utilization of your design. The Intel® Quartus® Prime software includes the Design Assistant design rule checking tool to help avoid design rule violations. These rules include Hyper-Retimer Readiness Rules (HRR) that specifically target Intel® Hyperflex™ architecture FPGA designs, as Design Assistant Design Rule Checking describes.