Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 12/08/2023
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2.3.2.2.4. (Optional) Auto-Pipeline Insertion without a Variable Latency Module

You can optionally enable auto-pipeline insertion, without use of the variable latency module (hyperpipe_vlat) by following these steps for the target registers:
  1. To specify the maximum number of stages to insert, click Assignments > Assignment Editor, and then select Maximum Additional Pipelining for Assignment Name, enter the maximum number of pipelines for Value, and the hierarchical path to the register for To. Alternatively, you can add the following equivalent assignment to the .qsf.
    set_instance_assignment -name HYPER_RETIMER_ADD_PIPELINING \
         <maximum stages> -to <register path>
    Note: If you embed the assignment in RTL with the altera_attribute statement, rather than adding to the .qsf, you must specify the numeric value as a string in Verilog HDL and VHDL.
  2. To prevent any optimization of the bus before auto-pipelining inserts additional stages, specify the preserve pragma, and set Netlist Optimizations to Never Allow for the target registers in the Assignment Editor or with the following .qsf assignment. Any optimization of the bus before autopipelining can impact the signal integrity of if autopipelining adds additional stages to some but not all bits of the bus.
    set_instance_assignment -name \
         ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW -to <register path>
    
  3. To ensure that related registers receive the same number of additional pipeline stages, create an assignment group to associate and assign all registers in the group. If you do not define an assignment group, the group names auto-generate with a prefix of add_pipelining_group, and each register that you specify for HYPER_RETIMER_ADD_PIPELINING becomes a group.

    The following line shows the syntax of the .qsf group assignment:

    set_instance_assignment -name \
        HYPER_RETIMER_ADD_PIPELINING_GROUP <group name string> \
        -to <register path>