Intel® Hyperflex™ Architecture High-Performance Design Handbook

ID 683353
Date 12/08/2023
Public
Document Table of Contents

2.2.1.1. Removing Asynchronous Resets

Remove asynchronous resets if a circuit naturally resets when reset is held long enough to reach a steady-state equivalent of full reset.

Verilog HDL and VHDL Asynchronous Reset Examples shows how the asynchronous reset (shown in bold) resets all registers in the pipeline, preventing placement in Hyper-Registers.

Table 3.  Verilog HDL and VHDL Asynchronous Reset Examples
Verilog HDL VHDL
always @(posedge clk, aclr)
   if (aclr) begin
      reset_synch <= 1'b0;
      aclr_int <= 1’b0;
   end
   else begin
      reset_synch <= 1'b1;
      aclr_int <= reset_synch;
   end

always @(posedge clk, aclr_int)
// Asynchronous reset===============
   if (!aclr_int) begin
      a <= 1'b0;
      b <= 1'b0;
      c <= 1'b0;
      d <= 1'b0;
      out <= 1'b0;
   end
//===============
   else begin
      a <= in;
      b <= a;
      c <= b;
      d <= c;
      out <= d;
   end
PROCESS(clk, aclr) BEGIN
   IF (aclr = '0') THEN
      reset_synch <= '0';
      aclr_int <= '0';
   ELSIF rising_edge(clk) THEN
      reset_synch <= '1';
      aclr_int <= reset_synch;
   END IF;
END PROCESS;

PROCESS(clk, aclr_int) BEGIN
// Asynchronous reset===============
   IF (aclr_int = '0') THEN
      a <= '0';
      b <= '0';
      c <= '0';
      d <= '0';
      output <= '0';
//===============
   ELSIF rising_edge(clk) THEN
      a <= input;
      b <= a;
      c <= b;
      d <= c;
      output <= d;
   END IF;
END PROCESS;

Circuit with Full Asynchronous Reset shows the logic of Verilog HDL and VHDL Asynchronous Reset Examples in schematic form. When aclr is asserted, all the outputs of the flops are zeros. Releasing aclr and applying two clock pulses causes all flops to enter functional mode.

Figure 7.  Circuit with Full Asynchronous Reset

Partial Asynchronous Reset illustrates the removal of asynchronous resets from the middle of the circuit. After a partial reset, if the modified circuit settles to the same steady state as the original circuit, the modification is functionally equivalent.

Figure 8. Partial Asynchronous Reset


Circuit with an Inverter in the Register Chain shows how circuits that include inverting logic typically require additional synchronous resets to remain in the pipeline.

Figure 9. Circuit with an Inverter in the Register Chain

After removing reset and applying the clock, the register outputs do not settle to the reset state. If the asynchronous reset is removed from the inverting register, the circuit cannot remain equivalent with Circuit with an Inverter in the Register Chain after settling out of reset.

Figure 10. Circuit with an Inverter in the Register Chain with Asynchronous Reset


To avoid resetting logic caused by non-naturally inverting functions, validate the output to synchronize with reset removal, as Validating the Output to Synchronize with Reset illustrates. If the validating pipeline can enable the output when the computational pipeline is actually valid, the behavior is equivalent with reset removal. This method is suitable even if the computation portion of the circuit does not naturally reset.

Figure 11. Validating the Output to Synchronize with Reset

Verilog HDL Example Using Minimal or No Asynchronous Resets shows Verilog HDL and VHDL examples of Partial Asynchronous Reset. You can adapt this example to your design to remove unnecessary asynchronous resets.

Table 4.  Verilog HDL Example Using Minimal or No Asynchronous Resets
Verilog HDL VHDL
always @(posedge clk, aclr)
   if (aclr) begin
      reset_synch_1 <= 1'b0;
      reset_synch_2 <= 1'b0;
      aclr_int <= 1'b0;
   end
   else begin
      reset_synch_1 <= 1'b1;
      reset_synch_2 <= reset_synch_1;
      aclr_int <= reset_synch_2;
   end

// Asynchronous reset for output register=====
always @(posedge clk, posedge aclr_int)
   if (aclr_int)
      out <= 1'b0;
   else
      out <= d;



// Synchronous reset for input register=====
always @(posedge clk)
   if (reset_synch_2)
      a <= 1'b0;
   else
      a <= in;





// Naturally resetting registers=====
always @(posedge clk) begin
   b <= a;
   c <= b;
   d <= c;

end
PROCESS (clk, aclr) BEGIN
   IF (aclr = '1') THEN
      reset_synch_1 <= '0';
      reset_synch_2 <= '0';
      aclr_int <= '0';
   ELSIF rising_edge(clk) THEN
      reset_synch_1 <= '1';
      reset_synch_2 <= reset_synch_1;
      aclr_int <= reset_synch_2;
   END IF;
END PROCESS;

// Asynchronous reset for output register=====
PROCESS (clk, aclr_int) BEGIN
   IF (aclr_int = '1') THEN
      output <= '0';
   ELSIF rising_edge(clk) THEN
      output <= d;
   END IF;
END PROCESS;

// Synchronous reset for input register=====
PROCESS (clk) BEGIN
   IF rising_edge(clk) THEN
      IF (reset_synch_2 = '1') THEN
         a <= '0';
      ELSE
         a <= input;
      END IF;
   END IF;
END PROCESS;

// Naturally resetting registers=====
PROCESS (clk) BEGIN
   IF rising_edge(clk) THEN
      b <= a;
      c <= b;
      d <= c;
   END IF;
END PROCESS;