Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 2/15/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

19.3.2. TMO IP Latency

The latency information can predict the approximate latency between the input and the output of your video processing pipeline.

Table 281.  TMO LatencyThe table shows latency as a number of valid clock cycles. Intel measures the latency assuming that other functions are not stalling the IP on the datapath (the output ready signal is high).
Mode Latency (cycles)
Processing or bypass