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1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. Chroma Resampler Intel® FPGA IP 10. Clipper Intel® FPGA IP 11. Clocked Video to Full Raster Converter Intel® FPGA IP 12. Color Space Converter Intel® FPGA IP 13. Full Raster to Clocked Video Converter Intel FPGA IP 14. Full Raster to Streaming Converter Intel® FPGA IP 15. Guard Bands Intel® FPGA IP 16. Mixer Intel FPGA IP 17. Pixels in Parallel Converter IP 18. Scaler 19. Tone Mapping Operator Intel® FPGA IP 20. Test Pattern Generator Intel FPGA IP 21. Video Frame Buffer Intel FPGA IP 22. Video Streaming FIFO Intel FPGA IP 23. Warp Intel® FPGA IP 24. Document Revision History for Video and Vision Processing Suite User Guide
10.1. About the Clipper IP
The IP crops an active area from a video stream and discards the remainder. To specify the active region, you provide offsets from each edge of the image, or a point to be the top-left corner of the active region, and the region's width and height.
The IP is available as full or lite variants. For more information on full and lite, refer to the Intel FPGA Streaming Video Protocol Specification. The clipper IP changes input resolutions by reading video and vision processing image information packets, or using the register interface for lite variants.
An Avalon memory-mapped interface allows you to change the clipping settings at run time. This interface is mandatory for lite variants.
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