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22.1. About the Video Streaming FIFO IP
The IP supports full and lite variants without selecting a parameter. The depth of the FIFO buffer must be a whole power of two. The depth parameter sets the number of beats of data that the FIFO holds. When full, the IP deasserts the input tready signal to hold the input stream and ensure no loss of data. When empty, the IP deasserts the output tvalid signal.
The IP supports both single and dual clocks. With a single clock both the input and output interfaces are on the same clock domain. With dual clocks the input and output interfaces are on different clock domains. Dual clocks allow the IP to be a clock domain crossing bridge compliant to the Intel FPGA streaming video protocol.
The internal logic IP is delivers high operating clock frequencies (in excess of 600 MHz on Intel Agilex family devices), but with relatively high latency around 5-10 clock cycles with a single clock and 10-20 cycles with dual clocks.
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