Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 2/15/2022

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8.3. 3D LUT IP Block Description

The 3D LUT IP accepts RGB-format video input from its Intel FPGA video streaming interface. It uses the most significant bits (MSBs) of the 3 color component inputs to retrieve data values from the contents of the LUT and the least significant bits (LSBs) to interpolate the final output value. An Avalon Memory-Mapped compatible CPU interface handles the run-time control and LUT programming.
Figure 14. 3D LUT IP block diagram

The address decoder converts the MSBs of the three input color components into read addresses for the LUT. If you turn on Double buffered, the IP adds a page offset to the address when selecting the second buffer via the CPU interface. Page-flip double buffering allows for instantaneous switching between LUTs.

The LUT RAM instantiates the on-chip memory containing the LUT. The 3D LUT cube vertices are divided across eight sub-RAMs to output the target sub-cube vertices in parallel. Enabling the second buffer doubles the memory depth of the LUT. Both buffers' contents are programmable via the CPU interface and can also be pre-initialized in the firmware via the 3D LUT IP GUI.

The tetrahedral interpolator uses a DSP efficient method to interpolate four of the LUT subcube vertices using the input LSBs. Part of the input MSBs determines which of the six tetrahedra in the target sub-cube contains the pixel.

The control register in the run-time control register map allows you to switch between the interpolated output and the bypass output.

Consider these points when integrating in a streaming video pipeline:

  • The IP controls buffer selection and output enable and only updates them at the start of each new frame.
  • The internal pipeline forwards control signals and is unaffected by changes to video resolution.
Figure 15. 3D LUT color transform examplesFrom top left: original, saturation, brightness increase, colorize (purple), colorize (green), desaturation