Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 2/15/2022

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Document Table of Contents

21.1. About the Video Frame Buffer IP

The IP buffers frames of video and can perform frame dropping and repeating to double or triple buffer frames. The IP stores frames in external memory, so the frame buffer has Avalon memory-mapped interfaces to allow connection to an external memory interface.

The frame buffer supports:

  • Progressive video only
  • Triple or double frame buffering
  • Auxiliary control packets. Local storage for up to 255. The IP can optionally drop and repeat auxiliary packets with their associated frame.
  • Maximum frame resolutions of 16384 by 16384 pixels with 1 to 8 pixels in parallel and any color space
  • Configurable memory packing scheme
  • Optional dropping of broken frames
  • Frame statistics counters

The IP is available as full or lite variants. For more information on full and lite, refer to the Intel FPGA Streaming Video Protocol Specification. The Video Frame Buffer IP takes input resolution information from image information packets or using the register interface for lite variants.

An Avalon memory-mapped interface allows you to read frame statistics and turn the frame buffer output off and on at run time. You must have this interface for lite variants.

For details about latency and reset behavior for the Video Frame Buffer, refer to Video and Vision IPs Functional Description.