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1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. Chroma Resampler Intel® FPGA IP 10. Clipper Intel® FPGA IP 11. Clocked Video to Full Raster Converter Intel® FPGA IP 12. Color Space Converter Intel® FPGA IP 13. Full Raster to Clocked Video Converter Intel FPGA IP 14. Full Raster to Streaming Converter Intel® FPGA IP 15. Guard Bands Intel® FPGA IP 16. Mixer Intel FPGA IP 17. Pixels in Parallel Converter IP 18. Scaler 19. Tone Mapping Operator Intel® FPGA IP 20. Test Pattern Generator Intel FPGA IP 21. Video Frame Buffer Intel FPGA IP 22. Video Streaming FIFO Intel FPGA IP 23. Warp Intel® FPGA IP 24. Document Revision History for Video and Vision Processing Suite User Guide
1.3. Video and Vision Processing IPs Features
- Intel FPGA streaming video data interfaces for video I/O, based on the industry standard AXI4-Stream protocol
- Avalon memory-mapped agent interfaces for run-time control and Avalon memory-mapped host interface for external memory usage allowing push-button conversion in Intel Platform Designer to industry standard AXI4 or AXI4-Lite memory mapped interfaces if required.
- Device utilization and Fmax on Intel Agilex FPGAs allowing 8K60 processing on Intel Agilex platforms with four pixels in parallel at 600 MHz.
- Processing flexibility of 1 to 8 pixels in parallel
- 1 to 4 color symbols per pixel with 1 to 8 pixels in parallel and RGB and YCbCr 444, 422 and 420 color spaces. The Intel FPGA streaming video protocol specification describes pixel packing.
- Data precision of from 8 to 16 bits per symbol.
- Video fields with 1 to 16384 pixels in both height and width.
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