Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 2/15/2022
Public

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Document Table of Contents

20.3.1. Test Pattern Generator IP Interfaces

Name Direction Width Description
Clocks and resets
main_clock_clk In 1 AXI4-S processing clock.
main_reset_rst In 1 AXI4-S processing reset.
agent_clock_clk In 1 Clock for the Avalon memory-mapped control agent interface. Only if you select separate clock for control interface.
agent_reset_rst In 1 Reset for the Avalon memory-mapped control agent interface. Only if you select separate clock for control interface.
Control interfaces
av_mm_control_agent_address In 7 Avalon memory-mapped agent address .
av_mm_control_agent_write In 1 Avalon memory-mapped agent write.
av_mm_control_agent_writedata In 32 Avalon memory-mapped agent write data.
av_mm_control_agent_byteenable In 4 Avalon memory-mapped agent byte enable.
av_mm_control_agent_read In 1 Avalon memory-mapped agent read.
av_mm_control_agent_readdata Out 32 Avalon memory-mapped agent read data.
av_mm_control_agent_readdatavalid Out 1 Avalon memory-mapped agent read.
av_mm_control_agent_waitrequest Out 1 Avalon memory-mapped agent wait request.

Intel FPGA streaming video interfaces

axi4s_vid_out_tdata Out 46 AXI4-S data in.
axi4s_vid_out_tvalid Out 1 AXI4-S data valid.
axi4s_vid_in_tuser Out 47

AXI4-S tuser

tuser[0] indicates start of video frame when asserted

tuser[1] indicates the start of a non-video packet when asserted.

axi4s_vid_out_tlast Out 1 AXI4-S end of packet .
axi4s_vid_out_tready In 1 AXI4-S data ready.
46

The equation gives all tdata widths in these interfaces:

max (ceil((bits per color sample x number of color planes x pixels in parallel) / 8) x 8, 16)

47

The equation gives all tuser widths in these interfaces

N = ceil (tdata width / 8)