Early Power Estimator User Guide

ID 683272
Date 7/16/2021
Document Table of Contents

2.3.2. Estimating Power Consumption While Creating the FPGA Design

If your FPGA design is partially complete, you can import the EPE file (<revision name> _early_pwr.csv) generated by the Intel® Quartus® Prime software to the EPE spreadsheet. After importing the information from the <revision name> _early_pwr.csv into the EPE spreadsheet, you can edit the EPE spreadsheet to reflect the device resource estimates for your final design.

Table 2.  Advantages and Constraints of Power Estimation if your FPGA Design is Partially Complete
Advantage Constraint
  • You can perform power estimation early in the FPGA design cycle.
  • Provides the flexibility to automatically fill in the Early Power Estimator spreadsheet based on the Intel® Quartus® Prime software compilation results.
  • Accuracy depends on your inputs and your estimation of the device resources; where this information may change (during or after your design is complete), your power estimation results may be less accurate.
  • The EPE spreadsheet uses averages and not the actual design implementation details; for example ALUT input usage and routing. The Power Analyzer has access to the full design details.