Early Power Estimator User Guide

ID 683272
Date 7/16/2021
Document Table of Contents

2.3.1. Estimating Power Consumption Before Starting the FPGA Design

Table 1.  Advantage and Constraints of Power Estimation before Designing FPGA
Advantage Constraint
You can obtain power estimation before starting your FPGA design.
  • Accuracy depends on your inputs and your estimation of the device resources; where this information may change (during or after your design is complete), your power estimation results may be less accurate.
  • The EPE spreadsheet uses averages and not the actual design implementation details; for example ALUT input usage and routing. The Power Analyzer has access to the full design details.

To estimate power consumption with the EPE spreadsheet before starting your FPGA design, follow these steps:

  1. On the Main worksheet of the EPE spreadsheet, select the target family, device, and package from the Family, Device, and Package drop-down list.
  2. Enter values for each worksheet in the EPE spreadsheet. Different worksheets in the EPE spreadsheet display different power sections, such as clocks and phase-locked loops (PLLs).
  3. The calculator displays the total estimated power consumption in the Total FPGA and Total SoC (if applicable) cells of the Main worksheet.