Early Power Estimator User Guide

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ID 683272
Date 7/16/2021
Public
Document Table of Contents
Document Table of Contents x
1. Early Power Estimator Overview 2. Setting Up the Early Power Estimator 3. Early Power Estimator Worksheets 4. Factors Affecting the Early Power Estimator Spreadsheet Accuracy A. Additional Information for Early Power Estimator User Guide
1. Early Power Estimator Overview x
1.1. Release Information 1.2. Power Model Status for Supported Device Families
2. Setting Up the Early Power Estimator x
2.1. System Requirements 2.2. Download and Install the Early Power Estimator 2.3. Estimating Power Consumption
2.2. Download and Install the Early Power Estimator x
2.2.1. Changing the Macro Security Level in Microsoft Excel 2003 2.2.2. Changing the Macro Security Level in Microsoft Excel 2007 2.2.3. Changing the Macro Security Level in Microsoft Excel 2010
2.3. Estimating Power Consumption x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
2.3.1. Estimating Power Consumption Before Starting the FPGA Design x
2.3.1.1. Entering Information into the Early Power Estimator
2.3.1.1. Entering Information into the Early Power Estimator x
2.3.1.1.1. Manually Entering Values
2.3.2. Estimating Power Consumption While Creating the FPGA Design x
2.3.2.1. Importing a File
2.3.2.1. Importing a File x
2.3.2.1.1. Generate the EPE File 2.3.2.1.2. Import Data into the EPE Spreadsheet
3. Early Power Estimator Worksheets x
3.1. Main Worksheet 3.2. Logic Worksheet 3.3. RAM Worksheet 3.4. DSP Worksheet 3.5. I/O Worksheet 3.6. PLL Worksheet 3.7. Clock Worksheet 3.8. HSDI Worksheet 3.9. XCVR Worksheet 3.10. HMC Worksheet 3.11. IP Worksheet 3.12. HPS Worksheet 3.13. Report Worksheet 3.14. Enpirion Worksheet
3.1. Main Worksheet x
3.1.1. Input Parameter 3.1.2. Thermal Power 3.1.3. Power Tree Design 3.1.4. Thermal Analysis
3.1.4. Thermal Analysis x
3.1.4.1. Not Using a Heat Sink 3.1.4.2. Using a Heat Sink
3.13. Report Worksheet x
3.13.1. Static Power and Dynamic Current per Voltage Rail 3.13.2. Power Up Current 3.13.3. Power Breakout for Multiple Voltage Supplies 3.13.4. Power Regulator Settings
4. Factors Affecting the Early Power Estimator Spreadsheet Accuracy x
4.1. Toggle Rate 4.2. Airflow 4.3. Temperature 4.4. Heat Sink
A. Additional Information for Early Power Estimator User Guide x
A.1. Document Revision History for Early Power Estimator User Guide
1. Early Power Estimator Overview
2. Setting Up the Early Power Estimator
3. Early Power Estimator Worksheets
4. Factors Affecting the Early Power Estimator Spreadsheet Accuracy
A. Additional Information for Early Power Estimator User Guide

3.1.2. Thermal Power

Thermal power is the power dissipated in the device. Total thermal power is a sum of the thermal power of all the resources used in the device, including the maximum power from standby and dynamic power.

Total thermal power only includes the thermal component for the I/O section and does not include the external power dissipation, such as from voltage-referenced termination resistors.

The static power (PSTATIC) is the thermal power dissipated on chip, independent of user clocks. PSTATIC includes the leakage power from all FPGA functional blocks, except for I/O DC bias power and transceiver DC bias power, which are accounted for in the I/O and transceiver sections.

PSTATIC is the only thermal power component which varies with junction temperature, selected device, and power characteristics (process).

The following figure shows the total thermal power (W) and PSTATIC consumed by the FPGA and hard processor system (HPS). The thermal power for each worksheet is displayed. To see how the thermal power for a worksheet was calculated, click on the button to view the selected worksheet.

Figure 2. Thermal Power Section in the Main Worksheet
Table 4.  Thermal Power Section Information
Column Heading Description
Logic This value shows the dynamic power consumed by adaptive logic modules (ALMs) and associated routing. To view details, click the Logic button.
RAM This value shows the dynamic power consumed by RAM blocks and associated routing. To view details, click the RAM button.
DSP This value shows the dynamic power consumed by digital signal processing (DSP) blocks and associated routing. To view details, click the DSP button.
I/O This value shows the thermal power consumed by I/O pins and associated routing. To view details, click the I/O button.
HSDI This value shows the dynamic power consumed by serializer and deserializer (SERDES) hardware for high-speed differential I/O (HSDI). To view details, click the HSDI button.
PLL This value shows the dynamic power consumed by phase-locked loops (PLLs). To view details, click the PLL button.
Clock This value shows the dynamic power consumed by clock networks. To view details, click the Clock button.
HMC This value shows the dynamic power consumed by hard memory controller (HMC). To view details, click the HMC button.
XCVR

This shows the thermal power consumed by transceiver hardware. This includes the standby power consumed by transceivers.

To view details, click the XCVR button. If the value is N/A, the transceiver blocks are not available on the chosen device.

PCS and HIP

This shows the thermal power consumed by the transceiver channel physical coding sublayer (PCS) as well as the PCI Express® (PCIe®) hard IP blocks of the transceiver hardware. This includes the standby power consumed by transceivers.

To view details, click the PCS and HIP button. If the value is N/A, the transceiver blocks are not available on the chosen device.

PSTATIC

This shows the thermal power dissipated on chip, independent of user clocks. This includes the leakage power from all FPGA functional blocks, except for I/O DC bias power and transceiver DC bias power.

PSTATIC is affected by junction temperature, selected device, and power characteristics.

The static power for HPS is shown in PSTATIC,HPS.

Total FPGA This shows the total power dissipated as heat from the FPGA. This does not include power dissipated in off-chip termination resistors and HPS.
HPS This value shows the thermal power consumed by the HPS. To view the details, click the HPS button.
PSTATIC,HPS

This shows the thermal power dissipated from the HPS, independent of user clocks. This includes the leakage power from all HPS functional blocks, except for HPS I/O DC bias power.

PSTATIC,HPS is affected by junction temperature, selected device, and power characteristics. The static power for HPS will be turned on once the SoC device is selected.

Total SoC This value shows the total power dissipated as heat from the FPGA and HPS. This value does not include power dissipated in off-chip termination resistors.
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