AN 556: Using the Design Security Features in Intel FPGAs

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ID 683269
Date 5/21/2021
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Internal JTAG Interface

There are two interfaces to access the JTAG control block in 28-nm and 20-nm FPGAs: the external JTAG interface and the internal JTAG interface.

The external JTAG interface accesses the JTAG control block through the physical JTAG pins—TCK, TDI, TDO, and TMS. You use the external JTAG interface for FPGA configuration when using JTAG configuration scheme via programming cables or executing JTAG instructions using external player or processor such as JAM player or JTAG chain debugger tool. The internal JTAG interface refers to the connection between TCK, TDI, TDO, and TMS signals from the internal FPGA core fabric and the JTAG control block.

You can only access the JTAG control block using either one of these interfaces one at a time. For example, when you use the internal JTAG interface, the external JTAG interface to the JTAG control block is disabled. To access the internal JTAG interface, you must include the WYSIWYG atom in your Intel® Quartus® Prime design.

Figure 3. Internal and External JTAG Interface Connection


Table 18.  WYSIWYG Atom for 28-nm and 20-nm FPGAs
Device Family JTAG WYSIWYG Atom
Arria® V
arriav_jtag <jtagblock_name>
(
.clkdruser(),
.corectl(),
.runidleuser(),
.shiftuser(),
.tck(),
.tckcore(),
.tckutap(),
.tdi(),
.tdicore(),
.tdiutap(),
.tdo(),
.tdocore(),
.tdouser(),
.tdoutap(),
.tms(),
.tmscore(),
.tmsutap(),
.updateuser(),
.usr1user()
);
Cyclone® V
cyclonev_jtag <jtagblock_name>
(
.clkdruser(),
.corectl(),
.runidleuser(),
.shiftuser(),
.tck(),
.tckcore(),
.tckutap(),
.tdi(),
.tdicore(),
.tdiutap(),
.tdo(),
.tdocore(),
.tdouser(),
.tdoutap(),
.tms(),
.tmscore(),
.tmsutap(),
.updateuser(),
.usr1user()
);
Stratix® V
stratixv_jtag <jtagblock_name>
(
.clkdruser(),
.corectl(),
.runidleuser(),
.shiftuser(),
.tck(),
.tckcore(),
.tckutap(),
.tdi(),
.tdicore(),
.tdiutap(),
.tdo(),
.tdocore(),
.tdouser(),
.tdoutap(),
.tms(),
.tmscore(),
.tmsutap(),
.updateuser(),
.usr1user()
);
Intel® Arria® 10
twentynm_jtag <jtagblock_name>
(
.tms(),
.tck(),
.tdi(),
.ntrst(),
.tdoutap(),
.tdouser(),
.tmscore(),
.tckcore(),
.tdicore(),
.ntrstcore(),
.tmscorehps(),
.tckcorehps(),
.tdicorehps(),
.ntrstcorehps(),
.tdocorefrwl(),
.corectl(),
.ntdopinena(),
.tdo(),
.tmsutap(),
.tckutap(),
.tdiutap(),
.ntrstutap(),
.tmsuhps(),
.tckuhps(),
.tdiuhps(),
.ntrstuhps(),
.tmscoreout(),
.tckcoreout(),
.tdocorehps(),
.ntrstcoreout(),
.shiftuser(),
.clkdruser(),
.updateuser(),
.runidleuser(),
.usr1user(),
.tdocore(),
);
Intel® Cyclone® 10 GX
twentynm_jtag <jtagblock_name>
(
.tms(),
.tck(),
.tdi(),
.ntrst(),
.tdoutap(),
.tdouser(),
.tmscore(),
.tckcore(),
.tdicore(),
.ntrstcore(),
.tdocorefrwl(),
.corectl(),
.ntdopinena(),
.tdo(),
.tmsutap(),
.tckutap(),
.tdiutap(),
.ntrstutap(),
.tmscoreout(),
.tckcoreout(),
.tdocorehps(),
.ntrstcoreout(),
.shiftuser(),
.clkdruser(),
.updateuser(),
.runidleuser(),
.usr1user(),
.tdocore(),
);
Table 19.  Functions of the Ports in WYSIWYG Atom
Ports Input/Output Functions
<jtagblock_name>

Identifier for the arriaii_jtag WYSIWYG atom and represents any identifier name that is legal for the given description language, such as Verilog HDL, VHDL, and AHDL.

.corectl() Input

Active high input to the JTAG control block to enable the internal JTAG access from core interface. When the FPGA enters user mode after configuration, this port is low by default. Pulling this port to logic high enables the internal JTAG interface (with external JTAG interface disabled at the same time) and pulling this port to logic low disables the internal JTAG interface (with external JTAG interface enabled at the same time).

.tckcore() Input Core TCK signal. 19
.tdicore() Input Core TDI signal. 19
.tdocore() Output Core TDO signal. 19
.tmscore() Input Core TMS signal. 19
.clkdruser() Input/Output

These ports are not used for enabling the JTAG secure mode using the internal JTAG interface, hence you can leave them unconnected.

.runidleuser()
.shiftuser()
.tck()
.tckutap()
.tdi()
.tdiutap()
.tdo()
.tdouser()
.tdoutap()
.tms()
.tmsutap()
.updateuser()
.usr1user()
19 For external JTAG interface, refer to the respective device datasheet for the JTAG configuration timing specification. For internal JTAG interface, you must perform timing constraint and timing closure analysis on these paths to meet the setup or hold time requirement.

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