JTAG Secure Mode for 28-nm and 20-nm FPGAs
FPGAs are in JTAG Secure mode upon power up when you:
- Enable the tamper-protection bit for 28-nm FPGAs
- Enable the JTAG Secure settings for 20-nm FPGAs
During JTAG secure mode, many JTAG instructions are disabled. The 28-nm and 20-nm FPGAs in JTAG secure mode only allow you to exercise mandatory IEEE Std. 1149.1 and IEEE Std. 1149.6 BST JTAG instructions. If you attempt to exercise a non-mandatory JTAG instruction when the FPGA is in the JTAG secure mode, the BYPASS JTAG instruction chain is selected and the instruction is not executed.
|Mandatory IEEE Std. 1149.1 and IEEE Std. 1149.6 BST JTAG Instructions
|Non-Mandatory IEEE Std. 1149.1 and IEEE Std. 1149.6 BST JTAG Instructions
For 28-nm FPGAs, to enable the access of non-mandatory JTAG instructions, you must issue the UNLOCK JTAG instruction to deactivate the JTAG secure mode. You can issue the LOCK instruction to put the device back into JTAG secure mode. You can only issue both the LOCK and UNLOCK JTAG instructions during user mode using internal JTAG interface. Issuing these two instructions using the external JTAG pins does not activate or deactivate the JTAG secure mode.
The LOCK and UNLOCK JTAG instructions only activate or deactivate the JTAG secure mode on an FPGA with tamper-protection bit enabled. Issuing these two instructions on a device that has a tamper-protection bit disabled does not turn on or turn off the JTAG secure mode.