AN 556: Using the Design Security Features in Intel FPGAs

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ID 683269
Date 5/21/2021
Public
Document Table of Contents
Document Table of Contents x
Using the Design Security Features in Intel® FPGAs
Using the Design Security Features in Intel® FPGAs x
Overview of the Design Security Feature Hardware and Software Requirements Steps for Implementing a Secure Configuration Flow Steps to Enable Tamper-Protection Bit Programming Supported Configuration Schemes Security Mode Verification Serial Flash Loader Support with Encryption Enabled Serial Flash Loader Support with Encryption Enabled for Single FPGA Device Chain JTAG Secure Mode for 28-nm and 20-nm FPGAs Document Revision History for AN 556: Using the Design Security Features in Intel® FPGAs
Overview of the Design Security Feature x
Security Encryption Algorithm Non-Volatile and Volatile Key Storage Key Programming Intel® Arria® 10 and Intel® Cyclone® 10 GX Qcrypt Security Tool
Intel® Arria® 10 and Intel® Cyclone® 10 GX Qcrypt Security Tool x
Using Qcrypt Tool Qcrypt Tool Options Security Levels of Qcrypt Tool Security Option
Hardware and Software Requirements x
Hardware Requirements Software Requirements
Steps for Implementing a Secure Configuration Flow x
Step 1: Generating .ekp File and Encrypting Configuration File Step 2a: Programming Volatile Key into the FPGAs Step 2b: Programming Non-Volatile Key into the FPGAs Step 3: Configuring the 40-nm, 28-nm, or 20-nm FPGAs with Encrypted Configuration Data
Step 1: Generating .ekp File and Encrypting Configuration File x
Generating Single-Device .ekp File and Encrypting Configuration File using Intel® Quartus® Prime Software Generating Single-Device .ekp File and Encrypting Configuration File using Command-Line Interface in Intel® Quartus® Prime Software Generating Multi-Device .ekp File and Encrypting Configuration File using Intel® Quartus® Prime Software
Step 2b: Programming Non-Volatile Key into the FPGAs x
Programming Volatile or Non-Volatile Key using Intel® FPGA Ethernet Cable and Intel® Quartus® Prime Software Programming Single-Device Volatile or Non-Volatile Key using Intel® Quartus® Prime Software Programming Single-Device Volatile or Non-Volatile Key using the Command-Line Interface in Intel® Quartus® Prime Software Programming Multi-Device Volatile or Non-Volatile Key using Intel® Quartus® Prime Software Programming Multi-Device Volatile or Non-Volatile Key using the Command-Line Interface in Intel® Quartus® Prime Software Programming Key using JTAG Technologies
Security Mode Verification x
Verification During JTAG Secure Mode
JTAG Secure Mode for 28-nm and 20-nm FPGAs x
Internal JTAG Interface Design Example for JTAG Secure Mode
Design Example for JTAG Secure Mode x
Design Example Intel® Quartus® Prime Design Components LOCK and UNLOCK JTAG Instructions Verifying JTAG Secure Mode
Using the Design Security Features in Intel® FPGAs

JTAG Secure Mode for 28-nm and 20-nm FPGAs

FPGAs are in JTAG Secure mode upon power up when you:

  • Enable the tamper-protection bit for 28-nm FPGAs
  • Enable the JTAG Secure settings for 20-nm FPGAs
Attention: 20-nm FPGAs do not support LOCK and UNLOCK JTAG instructions, you are not able to unlock external JTAG to access non-mandatory JTAG instructions.

During JTAG secure mode, many JTAG instructions are disabled. The 28-nm and 20-nm FPGAs in JTAG secure mode only allow you to exercise mandatory IEEE Std. 1149.1 and IEEE Std. 1149.6 BST JTAG instructions. If you attempt to exercise a non-mandatory JTAG instruction when the FPGA is in the JTAG secure mode, the BYPASS JTAG instruction chain is selected and the instruction is not executed.

Table 17.  Mandatory and Non-Mandatory IEEE Std. 1149.1 and IEEE Std. 1149.6 BST JTAG Instructions
Mandatory IEEE Std. 1149.1 and IEEE Std. 1149.6 BST JTAG Instructions Non-Mandatory IEEE Std. 1149.1 and IEEE Std. 1149.6 BST JTAG Instructions
  • BYPASS
  • EXTEST
  • IDCODE
  • LOCK
  • UNLOCK
  • SAMPLE/PRELOAD
  • SHIFT_EDERROR_REG
  • CONFIG_IO
  • CLAMP
  • EXTEST_PULSE 18
  • EXTEST_TRAIN 18
  • HIGHZ
  • KEY_CLR_VREG
  • KEY_VERIFY 18
  • PULSE_NCONFIG
  • USERCODE

For 28-nm FPGAs, to enable the access of non-mandatory JTAG instructions, you must issue the UNLOCK JTAG instruction to deactivate the JTAG secure mode. You can issue the LOCK instruction to put the device back into JTAG secure mode. You can only issue both the LOCK and UNLOCK JTAG instructions during user mode using internal JTAG interface. Issuing these two instructions using the external JTAG pins does not activate or deactivate the JTAG secure mode.

The LOCK and UNLOCK JTAG instructions only activate or deactivate the JTAG secure mode on an FPGA with tamper-protection bit enabled. Issuing these two instructions on a device that has a tamper-protection bit disabled does not turn on or turn off the JTAG secure mode.


Section Content
Internal JTAG Interface
Design Example for JTAG Secure Mode

18 You can execute these JTAG instructions during JTAG Secure mode for 20-nm FPGAs.
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