Design Example for JTAG Secure Mode
This design example demonstrates
- The instantiation of an internal JTAG WYSIWYG atom.
- The execution of the LOCK and UNLOCK JTAG instructions through user logic implementation in the Intel® Quartus® Prime software.
This reference design is targeted on the Arria V device with the tamper-protection bit enabled. This design example is applicable to other 28-nm FPGAs.
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