AN 556: Using the Design Security Features in Intel FPGAs

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ID 683269
Date 5/21/2021
Public
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Security Encryption Algorithm

Intel® FPGAs have a dedicated AES decryptor block than can decrypt configuration bit-streams prior to configuring the FPGA device. The 28-nm FPGAs use the AES block in CBC mode, while the 40-nm and 20-nm FPGAs use the AES block in CTR mode. In addition, the 20nm devices implement techniques to mitigate side-channel attacks against the standard NIST CTR mode of encryption. If the security feature is not used, the AES decryptor is bypassed. The FPGAs AES implementation is validated as conforming to the Federal Information Processing Standards FIPS-197.

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