Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 10/02/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.6.1. Concurrent Analysis During Synthesis or Fitting

If you run Analysis & Synthesis, or the Fitter, you can access results while downstream Fitter stages are still running. Once the Concurrent Analysis icons become active in the dashboard, you can view the analysis without interrupting compilation.

During Analysis & Synthesis, you can click the Concurrent Analysis icons on the Dashboard to view reports, the RTL Viewer, or the Technology Map Viewer. While the Fitter is processing, you can analyze timing during the stages displaying the Timing Analyzer icon, and view Technology Map Viewer snapshots during Fitter stages. You should not modify timing constraints during concurrent analysis, because it affects the results of the underlying compile. However, you can halt a compile at any time, modify the timing constraints in your .sdc file, and then click the Timing Analyzer icon to restart analysis with the modified constraints.

Figure 88. Concurrent Analysis Options