2.1.1. Compilation Flows
As you develop and optimize your design, run only the Compiler stages that you need, rather than waiting for full compilation. Run full compilation only when your design is complete and you are ready to run all Compiler modules and generate a device programming image.
|ECO Compilation Flow||The Intel® Quartus® Prime Pro Edition software supports last-minute, targeted design changes (also known as engineering change orders (ECOs)), even after you fully compile the design. ECOs typically occur during the design verification stage. Refer to the Intel® Quartus® Prime Pro Edition User Guide: Design Optimization.|
|Incremental Optimization Flow||Incremental optimization allows you to stop processing after each Fitter stage, analyze the results, and adjust settings or RTL before proceeding to the next compilation stage. This iterative flow optimizes at each stage, without waiting for full compilation results.|
|Hyper-Aware Design Flow||Combines automated register retiming (Hyper-Retiming), with implementation of targeted timing closure recommendations (Fast Forward Compilation), to maximize use of Hyper-Registers and drive the highest performance in Intel® Stratix® 10 and Intel Agilex® 7 devices.|
|Full Compilation Flow||Launches all Compiler modules in sequence to synthesize, fit, analyze final timing, and generate a device programming file. By default, the Compiler generates and preserves only the synthesized and final snapshots during a full compilation. You can optionally Enable Intermediate Fitter Snapshots to preserve the planned, placed, routed, and retimed snapshots.|
|Partial Reconfiguration||Reconfigures a portion of the FPGA dynamically, while the remaining FPGA design continues to function.|
|Block-Based Design Flows||Supports preservation and reuse of design blocks in one or more projects. You can reuse synthesized or final design blocks in other projects. Reusable design blocks can include device core or periphery resources.|