Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 10/02/2023

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2.3.5. Early Timing Analysis After Design Synthesis

The DNI-based Early Timing Analysis flow involves running Analysis & Elaboration and Synthesis stages and iterating on your design's static timing analysis results early in the Intel® Quartus® Prime software compilation flow without running the Fitter. For more information about DNI, refer to DNI-Based Compilation Flow.
Figure 36. Early Timing Analysis Flow

For additional information about each of the compilation stages listed in the above diagram, refer to the following topics:

You can now access the Timing Analyzer right after design synthesis in the DNI-based compilation dashboard, as shown in the following image:

Figure 37. Early Timing Analysis Stage

The Early Timing Analysis flow combines Synopsys* Design Constraint (SDC) on RTL and post-synthesis static timing analysis. The SDC-on-RTL component of the Early Timing Analysis supports the underlying technology to read the constraints early in the compilation flow and use them in the later stages of the Intel® Quartus® Prime compilation. However, you can run the flow even without RTL SDCs where you can view the synthesized timing netlist.

For more information, refer to Synopsys* Design Constraint (SDC) on RTL and Post-Synthesis Static Timing Analysis (STA).