2.3. Design Netlist Infrastructure
As a first step, applications and flow for Early Design Analysis have been enabled that unlock the following significant benefits:
- Comprehensive and interactive schematic visualization of an unaltered view of your design (RTL).
- Deeper and advanced design analysis with an intuitive and rich Tcl scripting interface.
- Faster design interactions with granular synthesis.
- Simplified and user-friendly constraint authoring by allowing SDC-on-RTL targets.
- Faster design iterations by SDC cleanup and early timing analysis with post-synthesis timing.
Starting from the 23.3 release, DNI compilation flow is available by default. It supports the Assembler to generate and download bit stream to the hardware. It is compatible with Signal Tap, various design flows (Partial Reconfiguration, black box incremental compile, and import/export flows), and simulation model generation.