2.1. Compilation Overview
|IP Generation||Identifies the status and version of IP components in the project. Reports outdated IP that require upgrade.|
|Analysis & Synthesis||
Synthesizes, optimizes, minimizes, and maps design logic to device resources. The "synthesized" snapshot preserves the results of this stage.
Analysis & Elaboration is a stage of Analysis & Synthesis. This stage checks for design file and project errors.
|Fitter (Place & Route)||
Assigns the placement and routing of the design to specific device resources, while honoring timing and placement constraints. The Fitter includes the following stages:
|Fast Forward Timing Closure Recommendations||Generates detailed reports that estimate performance gains achievable by making specific RTL modifications.|
|Timing Analysis||Analyzes and validates the timing performance of all design logic with the Timing Analyzer.|
|Power Analysis||Optional module that estimates device power consumption. Specify the electrical standard on each I/O cell and the board trace model on each I/O standard in your design.|
|Assembler||Converts the Fitter's placement and routing assignments into a programming image for the FPGA device.|
|EDA Netlist Writer||Generates output files for use in other EDA tools, as Integrating Other EDA Tools describes.|
- Added support for new features in supported FPGA devices.
- Added support for new devices.
- Efficiency and performance improvements.
- Improvements to compilation time and resource use of the design software.