22.214.171.124.3. Inspecting SDC-on-RTL Constraints
The Tcl console allows you to experiment conveniently with targeting constraints and the related syntax. The DNI netlist is read-only when accessed from the Tcl console, and constraint commands are not saved into the design database.
Once the Analysis & Elaboration compilation stage completes, you can load the project in the console (project_open <project_name>) and load the appropriate DNI netlist checkpoint using the dni::load_design -checkpoint "constrained" command. You can now perform tasks such as:
- Read a specific SDC file using the dni::read_sdc<file_name> command.
- Dump constraints using the dni::write_sdc command.
- Run constraint commands that are limited to the local session. For more information, refer to Creating Constraints in SDC-on-RTL SDC Files.
After Analysis & Elaboration, you can invoke the RTL Analyzer (Constrained mode) from the compilation dashboard. The RTL Analyzer GUI allows you to view the constraints on the design netlist. When you select a netlist object in the semantic viewer, you can view constraints targeting that object in the Property viewer. This helps ensure the constraints target the intended nodes in your RTL.
In the following example, when you select iopll_refclk[1:0] and right-click and select Display Individual Bits from its context-sensitive menu, the Connectivity Details pop-up window displays its ports. When you select one of the ports, constraints applied to the port are displayed in a separate Constraints tab, as shown in the following image:
Besides the constraints of the selected object, the Constraints tab also includes constraints of the associated object. For example, a net bus’ constraints are included along with the net's constraints, an instance bus’ constraints with the instance’s constraint, and so on.
You can also launch the Constraints dialog box (Tools > Object Constraints) from the RTL Analyzer menu to view a list of all constraints (assignments and timing-related SDC). It allows you to select an assignment or a constraint and cross-probe to its source file by right-clicking and selecting View in Source. The source file that contains the assignment or constraint launches in the Intel® Quartus® Prime GUI with the assignment line highlighted.
The Constraints GUI allows you to filter four types of constraints:
- Global Assignments: Assignments that are created with the set_global_assignment command.
- Source Assignments: Assignments embedded in source RTLs.
- Instance Assignments: Assignments created with the set_instance_assignment command.
- Timing Constraints (SDC): Constraints created through SDC-on-RTL. They usually appear in the Constrained view of the Analysis & Synthesis stage. If no SDC is read in, the Timing Constraints (SDC) option is disabled. This can happen in views before SDC are read in, for example, in "Elaborated" and "Instrumented" views of the Analysis & Synthesis stage or when no SDC-on-RTL file is read in.
You can filter the constraints further using the filtering field to view constraints matching the string. It supports filtering through command name, file name, and line number. You can also sort the constraints using the Command, File, and Line column header.
Through the context-sensitive menu of the Constraints GUI, you can view the selected constraints in its source file or the objects that it applies to.
You can view objects that a constraint apply to through the Show Constrained Objects option, which displays the Constrained Objects dialog. In the Constrained Objects, you can select the constrained object through its context-sensitive menu. This allows you to view the object's property in the Property Viewer. You can also apply a color to each constrained object by clicking Create Color Set.
Intel® Quartus® Prime Timing Analyzer
The Intel® Quartus® Prime Timing Analyzer uses industry-standard constraint and analysis methodology to report on all data required times, data arrival times, and clock arrival times for all register-to-register, I/O, and asynchronous reset paths in your design. The Timing Analyzer verifies that the required timing relationships are met for your design to function correctly and confirms actual signal arrival times against the constraints you specify. For more information about the Timing Analyzer, refer to the Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer .
Using the Timing Analyzer GUI or Tcl command console, you can load SDC-on-RTL constraints into the timing analysis session by running the read_sdc command. By default, the read_sdc command always loads SDC-on-RTL constraints, which happens before loading other conventional Intel® Quartus® Prime software SDC files (SDC_FILE or SDC_FILE -read_during_post_syn_and_not_post_fit_timing_analysis). To disable the loading of SDC-on-RTL constraints during the calls to read_sdc, use the read_sdc -no_import option or set the QSF variable ENABLE_IMPORT_SDC_DURING_READ_SDC to OFF.
During static timing analysis, you can load only the SDC-on-RTL SDC constraints using the import_sdc command. This is helpful when debugging issues you suspect are caused by SDC-on-RTL constraints.
Once you import the constraints using the read_sdc or import_sdc command, they become standard constraints in the Timing Analyzer. Standard constraint diagnostic reports (report_exceptions, report_sdc, and so on) operate on these constraints, and you can update the constraints for the current Timing Analyzer session using the existing Intel® Quartus® Prime timing analysis API commands.