50G Interlaken MegaCore Function User Guide

ID 683217
Date 9/20/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8.1.7. Lane Profile

The LANE_PROFILE parameter specifies the mapping of Interlaken lanes to transceiver logical channels on one side of the device.

This parameter is not available in IP core variations that target an Intel® Arria® 10 device.

The Interlaken lane order is fixed: Interlaken Lane 0 maps to the lowest numbered logical channel to which a lane is mapped; Interlaken Lane 1 maps to the next lowest numbered logical channel to which a lane is mapped; etc. You determine the side of the device outside the IP core, with pin assignments. Your pin assignments must be consistent with the value of the LANE_PROFILE parameter.

The default value of this parameter is 24'b000000_000000_101101_101101, for use with the CMU PLL. This lane profile specifies that the eight 50G Interlaken IP core Interlaken lanes map to the logical channels in the two bottom transceiver blocks that are consistent with use of the CMU PLL. These logical channels are logical channels 0, 2, 3, 5, 7, 9, 10, and 12.

If you want to use the ATX PLL, you can set this parameter to specify the use of the full bottom transceiver block and two channels from the adjacent transceiver block.