50G Interlaken MegaCore Function User Guide

ID 683217
Date 9/20/2022
Public

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6. 50G Interlaken IP Core Register Map

The 50G Interlaken IP core control registers are 32 bits wide and are accessible to you using the management interface, an Avalon-MM interface which conforms to the Avalon Interface Specifications. This table lists the registers available in the IP core. All unlisted locations are reserved.

Table 19.   50G Interlaken IP Core Register Map

Offset

Name

R/W

Description

9'h0

PCS_BASE

RO

[31:8] – Constant “HSi” ASCII for Arria® V and Stratix® V variants.

[31:8] – Constant “HSj” ASCII for Intel® Arria® 10 variant.

[7:0] – version number

Despite its name, this register does not encode the hard PCS base address.

9'h1

LANE_COUNT

RO

Number of lanes

9'h2

TEMP_SENSE

RO

Device temperature according to the internal temperature sensing diode.

[7:0] – the temperature in degrees Fahrenheit

[15:8] – the temperature in degrees Celsius

For example, when the temperature is 54 degrees Celsius (130 degrees Fahrenheit), the value of the register is 0x3682. To interpret this register value, you read 0x36 (decimal 54) to be the temperature in degrees Celsius, and you read 0x82 (decimal 130) to be the temperature in degrees Fahrenheit.

This register is invalid in the following IP core variations:

  • Variations that target an Intel® Arria® 10 device
  • Variations in which you turn off the hidden parameter Include Temp Sense

9'h3

ELAPSED_SEC

RO

[23:0] - Elapsed seconds since power up. The IP core calculates this value from the management interface clock (mm_clk) for diagnostic purposes. During continuous operation, this value rolls over every 194 days.

9'h4

TX_EMPTY

RO

[NUM_LANES–1:0] – Transmit FIFO status (empty)

9'h5

TX_FULL

RO

[NUM_LANES–1:0] – Transmit FIFO status (full)

9'h6

TX_PEMPTY

RO

[NUM_LANES–1:0] – Transmit FIFO status (partially empty)

9'h7

TX_PFULL

RO

[NUM_LANES–1:0] – Transmit FIFO status (partially full)

9'h8

RX_EMPTY

RO

[NUM_LANES–1:0] – Receive FIFO status (empty)

9'h9

RX_FULL

RO

[NUM_LANES–1:0] – Receive FIFO status (full)

9'hA

RX_PEMPTY

RO

[NUM_LANES–1:0] – Receive FIFO status (partially empty)

9'hB

RX_PFULL

RO

[NUM_LANES–1:0] – Receive FIFO status (partially full)

9'hC

REF_KHZ 1

RO

PLL reference clock frequency (kHz)

9'hD

RX_KHZ 1

RO

RX recovered clock frequency (kHz)

9'hE

TX_KHZ 1

RO

TX serial clock frequency (kHz)

9'hF

LANE_PROFILE

RO

[NUM_LANES–1:0] – Mask delineating the transceivers this IP core uses on the device. For example, if the FPGA has 24 lanes on one side of the device and the IP core uses the bottom eight transceivers, the mask would be 24'b000000_000000_000011_111111. .

This register is not available in IP core variations that target an Intel® Arria® 10 device.

9'h10

PLL_LOCKED

RO

In Intel® Arria® 10 devices: [0] – Transmit PLL lock indication.

In other device families: [Number of transceiver blocks–1:0] – Transceiver block transmit PLL n lock indication. One lock indicator per transceiver block. Bits that correspond to unused transceiver block PLLs are forced to 1.

9'h11

FREQ_LOCKED

RO

[NUM_LANES–1:0] – Clock data recovery is frequency locked on the inbound data stream

9'h12

LOOPBACK

RW

[NUM_LANES–1:0] – For each lane, write a 1 to activate internal TX to RX serial loopback mode, or write a 0 to disable the loopback for normal operation.

9'h13

RESET

RW

Bit 9 : 1 = Force lock to data mode

Bit 8 : 1 =Force lock to reference mode

Bit 7 : 1 = Synchronously clear the TX-side error counters and sticky flags

Bit 6 : 1 = Synchronously clear the RX-side error counters and sticky flags

Bit 5 : 1 =Program load mode: perform a sequence of DMA reads. Currently the IP core supports only the value of 1'b0, indicating a processor controls the read operations.

Bit 4 : 1 = Ignore the RX analog reset

Bit 3 : 1 = Reset the soft microcontroller

Bit 2 : 1 = Reset the transmitter and the receiver

Bit 1 : 1 = Reset the receiver

Bit 0 : 1 =Ignore RX digital resets

The normal operating state for this register is all zeroes, to allow automatic reset control. These bits are intended primarily for hardware debugging use. Bit 2 is a good general purpose soft reset. Bits 6 and 7 are convenient for monitoring long stretches of error-free operation.

9'h20

ALIGN

RO

Bit 12 : TX lanes are aligned

Bit 0 : RX lanes are aligned.

9'h21

WORD_LOCK

RO

[NUM_LANES–1:0] – Word (block) boundaries have been identified in the RX stream.

9'h22

SYNC_LOCK

RO

[NUM_LANES–1:0] – Metaframe synchronization has been achieved.

9'h23

CRC0

RO

4 bit counters indicating CRC errors in lanes 7,6,5,4,3,2,1,0.

These saturate at F, and you clear them by setting bit 6 in the RESET register.

9'h24

CRC1

RO

4 bit counters indicating CRC errors in lanes 15,14,13,12,11,10,9,8.

These will saturate at F, and you clear them by setting bit 6 in the RESET register.

9'h25

CRC2

RO

4 bit counters indicating CRC errors in lanes 23,22,21,20,19,18,17,16.

These will saturate at F, and you clear them by setting bit 6 in the RESET register.

9'h27

SH_ERR

RO

[NUM_LANES–1:0] – Sticky flag indicating a sync header (framing bit) error has occurred in the corresponding RX lane since this bit was last cleared through the RESET register.

9'h28

RX_LOA

RO

Bit [0] – Sticky flag indicating loss of RX side lane-to-lane alignment since this bit was last cleared through the RESET register. Typically, the IP core asserts this bit in case of a catastrophic problem such as one or more lanes going down.

9'h29

TX_LOA

RO

Bit [0] – Sticky flag indicating loss of TX side lane to lane alignment since this bit was last cleared through the RESET register. Typically, the IP core asserts this bit in case of a TX FIFO underflow / overflow caused by a significant deviation from the expected data flow rate through the TX PCS.

9'h30

PCS_6SEL

RO

Transceiver block selection for PCS test bus. (Factory use only).

9'h31

PCS_LNSEL

RO

Lane selection within transceiver block for PCS test bus. (Factory use only).

9'h32

PCS_TB

RO

PCS test bus. (Factory use only).

9'h33

Reserved

9'h34

RX_PRBS_DONE

RO

[NUM_LANES–1:0] – Indicates whether enough bits have been received on the corresponding RX lane for one complete pass through the PRBS polynomial.

9'h35

RX_PRBS_ERR

RO

[NUM_LANES–1:0] – Sticky flag that indicates whether a PRBS error has occurred on the corresponding RX lane after RX_PRBS_DONE has attained the value of 1.

9'h36

RX_PRBS_COUNT

RO

[7:0] – This eight-bit counter holds the number of words that had PRBS errors across all lanes. Saturates at the value of 0xFF.

9'h37

RX_PRBS_CTRL

RW

Bit [0] – If you set this bit to the value of 1, the IP core clears the RX_PRBS_DONE, RX_PRBS_ERR, and RX_PRBS_COUNT registers. Reset this bit to the value of 0 to capture new PRBS status.

9'h38

CRC32_ERR_INJECT

RW

[NUM_LANES–1:0] - When a bit has the value of 1, the IP core injects CRC32 errors on the corresponding TX lane. When it has the value of 0, the IP core does not inject errors on the TX lane. You must maintain each bit at the value of 1 for the duration of a Meta Frame, at least, to ensure that the IP core transmits at least one CRC32 error.

1 Intel® recommends that you use this register only during hardware operation. During simulation, you should not rely on the value in this register, because the amount of simulation time required for the IP core to provide consistent values in the REF_KHZ, RX_KHZ, and TX_KHZ registers is too long.